Reliable cache design with detection of gate oxide breakdown using BIST

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 2009, Pages 366-371

  Ahmed, Fahad ^a   Milor, Linda ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

6T-SRAM; ATOMIC LAYER; BREAKDOWN POINTS; CACHE DESIGN; DEVICE FAILURES; DEVICE SIZES; GATE LEAKAGES; GATE OXIDE; GATE OXIDE BREAKDOWN; GATE OXIDE THICKNESS; MEMORY REDUNDANCY; ON CHIPS; SRAM CELL;

DESIGN; STATIC RANDOM ACCESS STORAGE;

GATES (TRANSISTOR);

EID: 77951019768     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2009.5413131     Document Type: Conference Paper

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