A statistical approach for full-chip gate-oxide reliability analysis

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2008, Pages 698-705

  Chopra, Kaviraj ^a   Zhuo, Cheng ^a   Blaauw, David ^a   Sylvester, Dennis ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP LEVELS; CHIP RELIABILITIES; COMPUTATIONALLY EFFICIENT; CONVENTIONAL APPROACHES; GATE OXIDE BREAKDOWNS; GATE OXIDE RELIABILITIES; HUGE SAMPLES; KEY FACTORS; MONTE CARLO SIMULATIONS; OXIDE RELIABILITIES; OXIDE THICKNESSES; RELATIVE LOCATIONS; SPATIAL CORRELATIONS; STATISTICAL APPROACHES; STATISTICAL FRAMEWORKS; THICKNESS VARIATIONS; USEFUL LIFETIMES;

CLUSTER ANALYSIS; COMPUTER AIDED DESIGN; DIES; GATES (TRANSISTOR); INTEGRATED CIRCUITS; MONTE CARLO METHODS; QUALITY ASSURANCE; RANDOM VARIABLES; RELIABILITY ANALYSIS;

RELIABILITY;

EID: 57849125876     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2008.4681653     Document Type: Conference Paper

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