A methodology to improve timing yield in the presence of process variations

Proceedings - Design Automation Conference

Volumn , Issue , 2004, Pages 448-453

  Raj, Sreeja ^a   Vrudhula, Sarma B K ^a   Wang, Janet ^a  

^a UNIVERSITY OF ARIZONA   (United States)

Author keywords

Gate Sizing; Timing Analysis; Timing Yield

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; INTEGRATED CIRCUIT LAYOUT; MONTE CARLO METHODS; OPTIMIZATION; PARAMETER ESTIMATION; PROBLEM SOLVING; TIMING CIRCUITS;

GATE SIZING; PROCESS VARIATIONS; TIMING ANALYSIS; TIMING YIELD;

PROCESS CONTROL;

EID: 4444333242     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/996566.996694     Document Type: Conference Paper

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