Successive pad assignment algorithm to optimize number and location of power supply pad using incremental matrix inversion

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2, Issue , 2005, Pages 723-728

  Sato, Takashi ^a   Hashimoto, Masanori ^b   Onodera, Hidetoshi ^a  

^a KYOTO UNIVERSITY   (Japan)

^b OSAKA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; LOCATION; VOLTAGE CONTROL;

EQUIVALENT MATRICES; EQUIVALENT RESISTANCE; INCREMENTAL MATRIX INVERSIONS; PAD ASSIGNMENTS; POWER DISTRIBUTION NETWORK; SUCCESSIVE PAD ASSIGNMENTS; TOPOLOGICAL MODIFICATION; VOLTAGE SOURCE;

MATRIX ALGEBRA;

EID: 51449097297     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1120725.1121003     Document Type: Conference Paper

References (14)

1. SIA, International Technology Roadmapfor Semiconductors, 2003 Edition, Assembly and-Packaging; Interconnect.
2. A. Dalai, L. Lev, and S. Mitra, "Design of an efficient power distribution network for the UltraSPARC-I™rnicroprocessor," in Proc. ICCD, October 1995, pp. 118-123.
3. A. Dharchoudhury, R. Panda, D, Blaauw, and R. Vaidyanathan, "Design and analysis of power distribution networks in PowerPC™ microprocessors," in Proc. DAC, June 1998, pp. 738-743.
4. J. Kozhaya, S. Nassif, and F. N. Najm, "A multigrid-like technique for power grid analysis" IEEE Trans, on CAD, vol. 21, no. 10, pp. 11481160, October 1998.
5. Y,-M. Lee and C. C.-P. Chen, "The power grid transient simulation in linear time based on 3D altemating-direction-implicit method," in Proc. DATE, 2003, pp. 1020-1025.
6. H. Qian, S. R. Nasif, and S. S. Sapatnekar, "Random walks in a supply network," in Proc. DAC, June 2003, pp. 93-98
7. M. Pedram, K. Chaudhary, and E. Kuh, "UO pad assignment based on the circuit structure" in Proc. ICCD, October 199i, pp. 314-318.
8. A. H. Ajami, K. Banaerjee, A. Mehrotra, and M. Pefram, "Analysis of lR-drop scaling with implications for deep submicron p/g network designs," in Proc. 1SQED, May 2003, pp. 35-10.
9. M. Marek-Sadowska, "Pad assignment for power nets in VLSI circuits," IEEE Trwis. on CAD, vol. 6, no. 4, pp. 550-560, July 1987.
10. J. Oh and M. Pedram, "Multi-pad power/ground network design for uniform distribution of ground bounce," in Proceedings Design Automation Conference, June 1998, pp. 287-290.
11. M. Zhao, Y. Fu, V. Zolotov, S. Sundareswaran, and P. Panda, "Optimal placement of power supply pads and pins," in Proceedings Design Automation Conference, June 2004, pp. 165-170.
12. "GNU octave," http://www.octave.org/.
13. O. Schenk, M. Hagemann, and S. Rollin, "Recent advances in sparse linear solver technology for semiconductor device simulation matrices," in Proc. S1SPAD, September 2003, pp. 103-108.
14. O, Schenk and K, Gortner, "Solving unsymmetric sparse systems of linear equations with PARDISO," J. of Future Generation Computer Systems, vol. 20(3), pp. 475-487, 2004.