Partition-driven standard cell thermal placement

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 2003, Pages 75-80

  Chen, Guoqiang ^a   Sapatnekar, Sachin ^b  

^a SYNOPSYS INC   (United States)

^b University of Minnesota   (United States)

Author keywords

Partition; Placement; Standard cell; Temperature; Thermal model; VLSI

Indexed keywords

ALGORITHMS; HEURISTIC METHODS; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; SUBSTRATES;

THERMAL DISTRIBUTION;

INTEGRATED CIRCUITS;

EID: 0038716791     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/640000.640018     Document Type: Conference Paper

References (20)

1. K. Banerjee, A. Mehrotra, A. Sangiovanni-Vincentelli, and C. Hu, "On thermal effects in deep sub-micron VLSI interconnects," Proceedings of the ACM/IEEE Design Automation Conference, pp. 885-891, 1999.
2. C. Tsai and S. Kang, "Cell-level placement for improving subtrate thermal distribution," IEEE Transactions on Computer-Aided Design, Vol. 19, No. 2, pp. 253-266, Feb 2000.
3. C. Chu and D. F. Wong, "A matrix synthesis approach to thermal placement," IEEE Transactions on Computer-Aided Design, Vol. 17, No. 11, pp. 1166-1174, Nov 1998.
4. G. Ausiello et al., Complexity and Approximation: Combinatorial Optimization Problems and their Approximability, Berlin, Germany: Springer, 1999.
5. W. Sun and C. Sechen, "Efficient and effective placement for very large circuits," IEEE Transactions on Computer-Aided Design, Vol. 14, No. 3, pp. 349-359, March 1995.
6. J. Kleinhans, G. Sigl, F. Johannes, and K. Antreich, "GORDIAN: VLSI Placement by quadratic programming and slicing optimization," IEEE Transactions on Computer-Aided Design, Vol. 10, No. 3, pp. 356-365, March 1991.
7. C. J. Alpert, T. Chan, A. B. Kahng, I. Markov, and P. Mulet, "Faster minimization of linear wirelength for global placement," IEEE Transactions on Computer-Aided Design, Vol. 17, No. 1, pp.3-13, Jan 1998.
8. C. Alpert, J.-H. Huang, and A. B. Kahng, "Multilevel circuit partitioning," Proceedings of the ACM/IEEE Design Automation Conference, pp. 530-533, 1997.
9. G. Karypis, R. Aggarwal, V. Kumar, and S. Shekhar, "Multilevel hypergraph partitioning: application in VLSI design," Proceedings of the ACM/IEEE Design Automation Conference, pp. 526-529, 1997.
10. K. Zhong and S. Dutt, "Effective partition-driven placement with simultaneous level processing and global net views," Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, pp. 254-259, 2000.
11. G. Golub and C. F. Van Loan, Matrix Computation, Baltimore, MD: John Hopkins University Press, 1996.
12. R. Horn and C. Johnson, Matrix Analysis, Cambridge, UK: Cambridge University Press, 1985
13. U. Trottenberg, C. Oosterlee and A Schuller, Multigrid, New York: Academic Press, 2001.
14. C. M. Fiduccia and R. M. Mattheyses, "A Linear Time Heuristic for Improving Network Partitions," Proceedings of the ACM/IEEE Design Automation Conference, pp. 175-181, 1982.
15. A. E. Caldwell, A. B. Kahng, S. Mantik, I. L. Markov, and A. Zelikovsky, "On Wirelength Estimations for Row-Based Placement," IEEE Transactions on Computer-Aided Design, Vol. 18, No. 9, pp. 1265-1278, Sep 1999.
16. http://vlsicad.cs.ucla.edu/software/PDtools/.
17. A. E. Caldwell, A. B. Kahng, and I. L. Markov, "Design and Implementation of Move-Based Heuristics for VLSI Hypergraph Partitioning," ACM Journal of Experimental Algorithms, Vol. 5, 2000.
18. http://www.netlib.org/c/meschach/.
19. P. Madden, "Reporting of Standard Cell Placement Results," Proceedings of the International Symposium on Physical Design, pp. 30-35, 2001.
20. Y. Cheng and S. Kang, "A Temperature-Aware Simulation Environment for Reliable ULSI Chip Design," IEEE Transactions on Computer-Aided Design, Vol. 19, No. 10, pp. 1211-1220, Oct 2000.