TSV stress aware timing analysis with applications to 3D-IC layout optimization

Proceedings - Design Automation Conference

Volumn , Issue , 2010, Pages 803-806

  Yang, Jae Seok ^a   Athikulwongse, Krit ^b   Lee, Young Joon ^b   Lim, Sung Kyu ^b   Pan, David Z ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

3DIC; Mobility variation; Stress; Timing analysis; TSV

Indexed keywords

3DIC; CELL LIBRARY; CHIP-MANUFACTURING; COEFFICIENTS OF THERMAL EXPANSIONS; CRITICAL CELLS; CRITICAL PATH DELAYS; FILL MATERIALS; GEOMETRIC RELATIONS; IC LAYOUT; INDIVIDUAL CELLS; LAYOUT OPTIMIZATION; MOBILITY VARIATION; NETLIST; RADIAL STRESS; RELATIVE LOCATION; RISE AND FALL TIME; SOC INTEGRATION; STRESS CONTOURS; STRESS-INDUCED; TEST CASE; THROUGH-SILICON-VIA; TIMING ANALYSIS; TIMING VARIATIONS; TSV; WAFER STACKING;

COMPUTER AIDED DESIGN; ELECTRON MOBILITY; HOLE MOBILITY; OPTIMIZATION; PROGRAMMABLE LOGIC CONTROLLERS; SEMICONDUCTING SILICON COMPOUNDS; SILICON WAFERS; TENSILE STRESS; THERMAL EXPANSION; THREE DIMENSIONAL;

TIME MEASUREMENT;

EID: 77956216567     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1837274.1837476     Document Type: Conference Paper

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