Statistical estimation of leakage current considering inter- and intra-die process variation

Proceedings of the International Symposium on Low Power Electronics and Design

Volumn 2003-January, Issue , 2003, Pages 84-89

  Rao, R ^a   Srivastava, A ^a   Blaauw, D ^a   Sylvester, D ^a  

^a The Department of Civil and Environmental Engineering   (United States)

Author keywords

Benchmark testing; Circuit testing; Delay estimation; Integrated circuit modeling; Leakage current; MOS devices; Permission; Probability density function; Semiconductor device modeling; Threshold voltage

Indexed keywords

DIES; ELECTRONIC EQUIPMENT TESTING; INTEGRATED CIRCUIT TESTING; INTELLIGENT SYSTEMS; LOW POWER ELECTRONICS; MONTE CARLO METHODS; MOS DEVICES; POWER ELECTRONICS; PROBABILITY DENSITY FUNCTION; SEMICONDUCTOR DEVICE MODELS; SEMICONDUCTOR DEVICE TESTING; SEMICONDUCTOR DEVICES; THRESHOLD VOLTAGE;

BENCHMARK TESTING; CIRCUIT TESTING; DELAY ESTIMATION; INTEGRATED CIRCUIT MODELING; PERMISSION;

LEAKAGE CURRENTS;

EID: 1542269365     PISSN: 15334678     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/LPE.2003.1231840     Document Type: Conference Paper

References (21)

1. C. Hu, "Device and technology impact on low power electronics," Low Power Design Methodologies, ed. Jan Rabaey, Kluwer, pp. 21-35, 1996.
2. http://developer.intel.com/design/mobile/datashts
3. S. Sirichotiyakul, T. Edwards, C. Oh, J. Zuo, A. Dharchoudhury, R. Panda, and D. Blaauw, "Standby power minimization through simultaneous threshold voltage and circuit sizing," Proc. DAC, pp. 436-441, 1999.
4. Y. Ye, S. Borkar, and V. De, "A new technique for standby leakage reduction in high-performance circuits," Proc. Symposium on VLSI Circuits, pp. 40-41, 1998.
5. J. Halter and F. Najm, "A gate-level leakage power reduction method for ultra-low-power CMOS circuits," Proc. CICC, pp. 475-478, 1997.
6. S. Mutoh, T. Douseki, Y. Matsuya, T. Aoki, S. Shigematsu, and J. Yamada, "1-V power supply high-speed digital circuit technology with multithreshold voltage CMOS," IEEE Journal of Solid-State Circuits, vol. 30, pp. 847-854, Aug. 1995.
7. R.K. Krishnamurthy, A. Alvandpour, V. De, and S. Borkar, "High-performance and low-power challenges for sub-70nm microprocessor circuits," Proc. CICC, pp. 125-128, 2002.
8. P. Pant, V. De, and A. Chatterjee, "Device-circuit optimization for minimal energy and power consumption in CMOS random logic networks," Proc. DAC, pp. 403-408, 1997.
9. International Technology Roadmap for Semiconductors, 2001.
10. S. Narendra, V. De, S. Borkar, and A. Chandrakasan, "Full chip sub-threshold leakage power prediction model for sub-0.18um CMOS," Proc. ISLPED, pp. 19-23, 2002.
11. S. Tyagi et al, "A 130nm generation logic technology featuring 70nm transistors, dual Vt transistors and 6 layers of Cu interconnect," Proc. IEDM, pp. 567-570, 2000.
12. J. Kao, S. Narendra, and A. Chandrakasan, "Subthreshold leakage modeling and reduction techniques," Proc. ICCAD, pp. 141-148, Nov. 2002.
13. A. Srivastava, R. Bai, D. Blaauw, and D. Sylvester, "Modeling and analysis of leakage power considering within-die process variations," Proc. ISLPED, pp. 64-67, 2002.
14. A. Papoulis, Probability, Random Variables, and Stochastic Processes, McGraw-Hill Inc, New York, 1991.
15. A. Chandrakasan, W.J. Bowhill, and F. Fox, Design of high-performance microprocessor circuits, IEEE Press, 2001.
16. K.K. Ng, S.A. Eshraghi, and T.D. Stanik, "An improved generalized guide for MOSFET scaling," IEEE TED, vol.40, pp. 1893-1895, 1993.
17. Z. Chen, M. Johnson, L. Wei, and K. Roy, "Estimation of standby leakage power in CMOS circuits considering accurate modeling of transistor stacks," Proc. ISLPED, pp. 239-244, 1998.
18. N.C. Beaulieu, A.A. Abu-Dayya, and, P.J.McLane. "Comparison of methods of computing lognormal sum distributions and outages for digital wireless applications," IEEE International Conference on Communications, vol.3 pp.1270-1275,1994.
19. S.C. Schwartz and Y.S. Yeh, "On the distribution function and moments of power sums with lognormal components," Bell Systems Technical Journal, vol.61, pp.1441-1462, Sept. 1982.
20. N. Marlow, "A normal limit theorem for power sums of independent random variables," Bell Systems Technical Journal, vol.46, pp.2081-2090, Nov. 1967.
21. F. Brglez and H. Fujiwara, "A neutral netlist of 10 combinational benchmark circuits and a target translator in Fortran," Proc. International Symposium on Circuits and Systems, pp. 695-698, May 1989.