Study of the manufacturing feasibility of 1.5-nm direct-tunneling gate oxide MOSFET's: Uniformity, reliability, and dopant penetration of the gate oxide

IEEE Transactions on Electron Devices

Volumn 45, Issue 3, 1998, Pages 691-700

  Momose, Hisayo Sasaki ^a   Nakamura, Shin Ichi ^a   Ohguro, Tatsuya ^a   Yoshitomi, Takashi ^a   Morifuji, Eiji ^a   Morimoto, Toyota ^a   Katsumata, Yasuhiro ^a   Iwai, Hiroshi ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

Direct tunneling; Gate oxide; Leakage current; MOSFET; Reliability

Indexed keywords

ANNEALING; CAPACITORS; ELECTRIC BREAKDOWN OF SOLIDS; ELECTRON TUNNELING; GATES (TRANSISTOR); LEAKAGE CURRENTS; LSI CIRCUITS; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DOPING; SILICON WAFERS; TRANSMISSION ELECTRON MICROSCOPY; VOLTAGE MEASUREMENT;

DIRECT TUNNELING GATE OXIDES;

MOSFET DEVICES;

EID: 0032028948     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/16.661230     Document Type: Article

References (33)

1. H. S. Momose, M. Ono, T. Yoshitomi, T. Ohguro, S. Nakamura, M. Saito, and H. Iwai, "Tunneling gate oxide approach to ultra-high-current drive in small-geometry MOSFET's,"inIEDM Tech. Dig., 1994, pp. 593-596.
2. _, "1.5-nm direct-tunneling gate oxide Si MOSFET's,"IEEE Trans. Electron Devices, vol. 43, pp. 1233-1242, Aug. 1996.
3. H. S. Momose, E. Morifuji, T. Yoshitomi, T. Ohguro, M. Saito, T. Morimoto, Y. Katsumata, and H. Iwai., "High-frequency AC characteristics of 1.5-nm gate oxide MOSFET's,"inIEDM Tech. Dig., 1996, pp. 105-108.
4. H. S. Momose, M. Ono, T. Yoshitomi, T. Ohguro, S. Nakamura, M. Saito, and H. Iwai, "Prospects for low-power, high-speed MPU's using 1.5-nm direct-tunneling gate oxide MOSFET's,"Solid State Electron., vol. 41, no. 5, pp. 707-714, 1997.
5. M. Depas, R. Degraeve, T. Nigam, G. Groeseneken, and M. Heyns, "Reliability of ultrathin gate oxides below 3 nm in the direct tunneling regime,"inExt. Abstr. 1996 Int. Conf. Solid State Devices and Mater., pp. 533-535.
6. L. Manchanda, "Trends in gate dielectrics for GSI and beyond: Practical limits,"inAbstr. SEMICON Korea 97 Semiconduct. Tech. Symp., p. IV-56.
7. S.-H. Lo, D. A. Buchanan, Y. Taur, and W. Wang, "Quantummechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide n-MOSFET's,"IEEE Electron Devices Lett., vol. 18, pp. 209-211, May 1997.
8. M. R. Pinto, W. F. Brinkman, and W. W. Troutman, "The transistor's discovery and what's ahead,"inProc. 27th Europ. Solid-State Device Res. Conf., 1997, pp. 125-132.
9. The National Technology Roadmap for Semiconductors, Semiconductor Industry Assoc. 1994 Report, SEMATECH, Austin, TX.
10. H. R. Huff and R. K. Goodall, "Silicon wafer thermal processing: 300-mm issues,"Future Fab. Int., Issue 3, vol. 1, pp. 35-49, 1997.
11. B. Johnson, S. Mastroianni, T. Stanley, and D. Tüll, "300-mm Fab architecture,"Future Fab. Int., Issue 3, vol. 1, pp. 51-58, 1997.
12. T. Yoshitomi, T. Ohguro, M. Saito, M. Ono, E. Morifuji, H. S. Momose, and H. Iwai, "High-performance 0.15-μm single-gate Co salicide CMOS,"inDig. Tech. Papers, VLSI Symp. Technol, 1996, pp. 34-35.
13. 2 salicide CMOS technology thermally stable up to 1000 °C with high TDDB reliability,"inDig. Tech. Papers, VLSI Symp. Technol., 1997, pp. 101-102.
14. S. M. Sze, "Tunnel devices,"inPhysics of Semiconductor Devices, 2nd ed. New York: Wiley, 1981, ch. 9, p. 513.
15. T. Yoshida, D. Imafuku, J. L. Alay, S. Miyazaki, and M. Hirose, "Quantitative analysis of tunneling current through ultrathin gate oxides,"Jpn. J. Appl. Phys., vol. 34, pt. 2, no. 7B, pp. L903-L906, 1995.
16. K. Yamabe and K. Taniguchi, "Time-dependent dielectric breakdown of thin thermally grown SiO2 films,"IEEE Trans. Electron Devices, vol. ED-32, pp. 423-428, Feb. 1985.
17. 2 thermally grown on Si substrate,"inIEDM Tech. Dig., 1985, pp. 372-375.
18. S.-Y. Oh, S.-G. Choi, C. G. Sodini, and J. L. Moll, "Analysis of the channel inversion layer capacitance in the very thin-gate IGFET,"IEEE Electron Device Lett., vol. EDL-4, pp. 236-239, July 1983.
19. G. Baccarani and M. R. Wordeman, "Transconductance degradation in thin-oxide MOSFET's,"IEEE Trans. Electron Devices, vol. ED-30, pp. 1295-1304, Oct. 1983.
20. A. Toriumi, M. Yoshimi, M. Iwase, K. Taniguchi, and C. Hamaguchi, "Experimental determination of finite inversion layer thickness in thin gate oxide MOSFET's,"Surf. Sci, vol. 170, pp. 363-369, 1986.
21. M.-S. Liang, J. Y. Choi, P.-K. Ko, and C. Hu, "Inversion-layer capacitance and mobility of very thin gate-oxide MOSFET's,"IEEE Trans. Electron Devices, vol. ED-33, pp. 409-412, Mar. 1986.
22. 2 at direct tunneling voltages,"inIEDM Tech. Dig., 1994, pp. 609-612.
23. 2 breakdown model for very low voltage lifetime extrapolation,"IEEE Trans. Electron Devices, vol. 41, pp. 761-767, May 1994.
24. J. F. Verwey, "Nonavalanche injection of hot carriers into SiO2,"J. Appl. Phys., vol. 44, no. 6, pp. 2681-2687, 1973.
25. M.-S. Liang, C. Chang, W. Yang, C. Hu, and R. W. Brodersen, "Hot carriers induced degradation in thin gate oxide MOSFET's,"inIEDM Tech. Dig., 1985, pp. 186-189.
26. Y. Hiruta, H. Oyamatsu, H. S. Momose, H. Iwai, and K. Maeguchi, "Gate oxide thickness dependence of hot-carrier induced degradation on p-MOSFET's,"in19th Europ. Solid State Device Res. Conf., 1989, pp. 732-735.
27. J. Y.-C. Sun, C. Wong, Y. Taur, and C.-H. Hsu, "Study of boron penetration through thin oxide with p+ polysilicon gate,"inDig. Tech. Papers, VLSI Symp. Technol., 1989, pp. 17-18.
28. F. K. Baker, J. R. Pfiester, T. C. Mêle, H.-H. Tseng, P. J. Tobin, J. D. Hayden, C. D. Gunderson, and L. C. Parrillo, "The influence of fluorine on threshold voltage instabilities in p+ polysilicon gated p-channel MOSFET's,"inIEDM Tech. Dig., 1989, pp. 443-446.
29. + gate devices,"inIEDM Tech. Dig., 1989, pp. 447-450.
30. + gate p-channel MOSFET's,"inDig. Tech. Papers, VLSI Symp. Technol., 1990, pp. 111-112.
31. 2O ambient,"inIEDM Tech. Dig., 1990, pp. 425-428.
32. T. Morimoto, H. S. Momose, Y. Ozawa, K. Yamabe, and H. Iwai, "Effects of boron penetration and resultant limitations in ultrathin pureoxide and nitrided-oxide gate-films,"inIEDM Tech. Dig., 1990, pp. 429-432.
33. H. S. Momose, T. Morimoto, Y. Ozawa, K. Yamabe, and H. Iwai, "Electrical characteristics of rapid thermal nitrided-oxide gate n- and p-MOSFET's with less than 1 atom% nitrogen concentration,"IEEE Trans. Electron Devices, vol. 41, pp. 546-552, Apr. 1994.