Scalable methods for the analysis and optimization of gate oxide breakdown

Proceedings of the 11th International Symposium on Quality Electronic Design, ISQED 2010

Volumn , Issue , 2010, Pages 638-645

  Fang, Jianxin ^a   Sapatnekar, Sachin S ^a  

^a UNIVERSITY OF MINNESOTA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT FAILURES; CLOSED-FORM MODELS; FAILURE PROBABILITY; GATE OXIDE BREAKDOWN; GATE SIZING; OPTIMIZATION APPROACH; OXIDE RELIABILITY; POSYNOMIAL; SCALABLE METHODS; SCALING METHOD;

DIGITAL INTEGRATED CIRCUITS; OPTIMIZATION; SCALABILITY;

GATES (TRANSISTOR);

EID: 77952596529     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2010.5450507     Document Type: Conference Paper

References (13)

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