Variability driven gate sizing for binning yield optimization

Proceedings - Design Automation Conference

Volumn , Issue , 2006, Pages 959-964

  Davoodi, Azadeh ^a   Srivastava, Ankur ^a  

^a UNIVERSITY OF MARYLAND   (United States)

Author keywords

Gate sizing; Process variations; Speed binning

Indexed keywords

MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; NATURAL FREQUENCIES; OPTIMIZATION; STATISTICAL METHODS; TIMING DEVICES;

FABRICATED CHIPS; GATE SIZING; PROCESS VARIATIONS; SPEED BINNING;

ALGORITHMS;

EID: 34547142836     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1146909.1147152     Document Type: Conference Paper

References (19)

1. A. Agrawal, K. Chopra, D. Blaauw, and V. Zolotov. Circuit Optimization Using Statistical Static Timing Analysis. In DAC, pages 338-342, 2005.
2. A. Raychowdhury, S. Ghosh, and K. Roy. A Novel On-chip Delay Measurement Hardware for Efficient Speed-Binning. In IOLTS, July 2005.
3. C. Visweswariah , K. Ravindran , K. Kalafala , S. G. Walker , and S. Narayan. First-Order Incremental Block-Based Statistical Timing Analysis. In DAC, 2004.
4. D. Sinha, N. V. Shenoy, and H. Zhou. Statistical Gate Sizing for Timing Yield Optimization. In ICCAD, Nov. 2005.
5. H. Chang, V. Zolotov, S. Narayan, and C. Visweswariah. Parameterized Block-Based Statistical Timing Analysis with Non-Ga ussian Parameters and Nonlinear Delay Functions. In DAC, 2005.
6. http://www.mosek.com.
7. J. Fishburn and A. Dunlop. TILOS: A Posynomial Programming Approach to Transistor Sizing. In ICCAD, pages 326-328, 1985.
8. J. Singh, V. Nookala, Z. Luo, and S. Sapatnekar. Robust Gate Sizing by Geometric Programming. In DAC, pages 315-320, July 2005.
9. Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic. Digital Integrated Circuits. Prentice Hall.
10. K. Chopra, S. Shah, A, Srivastava, David Blaauw, and D. Sylvester. Parameteric Yield Maximization using Gate Sizing based on Efficient Statistical Power and Delay Gradient Computation. In ICCAD, Nov. 2004.
11. M. Mani, A. Devgana, and M. Orshansky. An Efficient Algorithm for Statistical Minimization of Total Power under Timing Yield Constraints. In DAC, July 2005.
12. M. R. Guthaus, N. Venkateswaran, C. Visweswariah, and V. Zolotov. Gate Sizing Using Incremental Parameterized Statistical Timing Analysis. In ICCAD, Nov. 2005.
13. R. J-B Wets. Stochastic Programs with Fixed Recourse: The Equivalent Deterministic Program. In SIAM Review, pages 309-339, July 1974.
14. S. Bhardwaj, S. B.. K. Vrdhula. Leakage Minimization of Nano-scale Circuits in the Presence of Systematic and Random Variations. In ICCAD, Nov. 2005.
15. S. Borkar, T. Karnik, S. Narendra, J. Tschanz, A. Keshavarzi, V. De. Parameter Variations and Impacts on Circuits and Microarchitecture. In DAC, 2003.
16. S. Boyd and L. Vandenberghe. Convex Optimization. Cambridge 2004.
17. S. Sapatnekar, V. B. Rao, P.M. Vaidya, and S. M. Kang. An Exact Solution to the Transistor Sizing Problem for CMOS Circuits Using Convex Optimization. In IEEE Transactions on CAD, pages 1621-1634, Nov. 1993.
18. V. Khandelwal, A. Srivastava. A General Framework for Accurate Statistical Timing Analysis Cons idering Correlations. In DAC, 2005.
19. Y. Cao, T. Sato, D. Sylvester, M. Orshansky, and C. Hu. New paradigm of predictive MOSFET and interconnect modeling for early circuit design. In Proc. of CICC, 2000.