Refined statistical static timing analysis through learning spatial delay correlations

Proceedings - Design Automation Conference

Volumn , Issue , 2006, Pages 149-154

  Lee, Benjamin N ^a   Wang, Li C ^a   Abadir, Magdy S ^b  

^a University of California   (United States)

^b FREESCALE SEMICONDUCTOR INC   (United States)

Author keywords

Bayesian learning; Delay correlations; Statistical timing

Indexed keywords

COMPUTER SIMULATION; LEARNING SYSTEMS; SILICON;

BAYESIAN LEARNING; DELAY CORRELATIONS; STATISTICAL TIMING;

STATISTICAL METHODS;

EID: 34347239371     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1146909.1146952     Document Type: Conference Paper

References (15)

1. H. Chang and S. S. Sapatnekar. Statistical timing analysis considering spatial correlations using a single PERT-like traversal. In Proc of ICCAD, 2003.
2. Vishal Khandelwal and Ankur Srivastava. A general framework for accurate statistical timing analysis considering correlations. In. DAC, 2005.
3. Assem Agarwal, David Blauuw, and Vladmir Zolotov. Statistical timing analysis for intra-die process variations with, spadal correlations. In ICCAD, 2003.
4. C. Amin, N. Menezes, K. Kilpatrick, F. Dartu, U. Choudhury, N. Hakim, and Y. Ismail. Statistical static timing analysis: How simple can we get. In DAC, 2005.
5. M. Orshansky and A. Bandyopadhyay. Fast statistical timing analysis handling arbitrary delay correlations. In Proc of DAC, 2004.
6. C. Visweswariah,et al. First-order incremental block-based statistical timing analysis. In Proc. of DAC, 2004.
7. Nagib Hakim Sani R. Naself, Duane Boning. The care and feeding of your statistical static timer. In ICCAD, 2005.
8. M. Orshansky, L. Milor. C. Hu. Characterization of spatial intraneld gate cd variability, its impact on circuit performance, and spatial mask-level correction. In IEEE Tran, on Semiconductor Manufacturing, Vol 1.7, No 1, 2- 11, 2004.
9. P. Friedberg, et. al. Modeling Within-Die Spatial. Correlation Effects for Process-Design Co-Optimization. Proc. of ISQED, 2005
10. Duane S. Boning and Sani Nassif. Models of process variations in device and interconnect. In Chap 6, Design of High Performance Microprocessor Circuits, edited by W. BowhillA. Chandrakasan and F. Fox, IEEE Press, 2000.
11. David J.C. Mackay. Information. Theory, Inference, and Learning Algorithms. Cambridge University Press, 2003.
12. Benjamin N Lee, Li-C. Wang, and Magdy S. Abadir. Reducing pattern delay variations for screening frequency dependent defects. In Proceedings of the 23rd IEEE VLSI Test Symposium, pages 153-160, 2005. IEEE Computer Society.
13. E. F. Schisterma, et al. Estimation of the correlation, coefficient using the Bayesian Approach and its applications for epidemiologic research BMC Medical Research Methodology, Vol 3, 2003.
14. X. Yang, B-K. Choi, and M. Sarrafzadeh. A Standard-Cell Placement Tool for Designs with High Row Utilization ICCD, Sep, 2002.
15. J.-J. Liou, et.al Enhancing Test Efficiency for Delay Fault Testing Using Multiple-Clocked Schemes DAC, pp. 371-374, Jun. 10-14, 2002