Thermal via placement in 3D ICs

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 2005, Pages 167-174

  Goplen, Brent ^a   Sapatnekar, Sachin ^a  

^a University of Minnesota   (United States)

Author keywords

3 D IC; 3 D VLSI; Finite element analysis; Placement; Routing; Temperature; Thermal gradient; Thermal optimization; Thermal via

Indexed keywords

ALGORITHMS; FINITE ELEMENT METHOD; HEAT RESISTANCE; TEMPERATURE DISTRIBUTION; THERMAL GRADIENTS; VLSI CIRCUITS;

3-D IC; 3-D VLSI; PLACEMENT; ROUTING; THERMAL OPTIMIZATION; THERMAL VIA;

INTEGRATED CIRCUITS;

EID: 28344443452     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1055137.1055171     Document Type: Conference Paper

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