-
1
-
-
0034841272
-
A practical methodology for early buffer and wire resource allocation
-
Las Vegas, NV, June
-
C. J. Alpert, J. Hu, S. S. Sapatnekar, and P. G. Villarrubia, "A practical methodology for early buffer and wire resource allocation," in Proc. Design Automation Conference, Las Vegas, NV, June 2001, pp. 189-194.
-
(2001)
Proc. Design Automation Conference
, pp. 189-194
-
-
Alpert, C.J.1
Hu, J.2
Sapatnekar, S.S.3
Villarrubia, P.G.4
-
2
-
-
0029342313
-
Primdijkstra tradeoffs for improved performance-driven routing tree design
-
July
-
C. J. Alpert, T. C. Hu, J. H. Huang, A. B. Kahng, and D. Karger, "Primdijkstra tradeoffs for improved performance-driven routing tree design," IEEE Trans. Computer-Aided Design, vol. 14, pp. 890-896, July 1995.
-
(1995)
IEEE Trans. Computer-aided Design
, vol.14
, pp. 890-896
-
-
Alpert, C.J.1
Hu, T.C.2
Huang, J.H.3
Kahng, A.B.4
Karger, D.5
-
4
-
-
0030704451
-
Power supply noise analysis methodology for deep-submicron VLSI chip design
-
Anaheim, CA, June
-
H. H. Chen and D. D. Ling, "Power supply noise analysis methodology for deep-submicron VLSI chip design," in Proc. Design Automation Conf., Anaheim, CA, June 1997, pp. 638-643.
-
(1997)
Proc. Design Automation Conf.
, pp. 638-643
-
-
Chen, H.H.1
Ling, D.D.2
-
5
-
-
0032136312
-
Interconnect and circuit modeling techniques for full-chip power supply noise analysis
-
Aug.
-
H. H. Chen and J. S. Neely, "Interconnect and circuit modeling techniques for full-chip power supply noise analysis," IEEE Trans. Comp., Packag., Manufact. Technol. B, vol. 21, pp. 209-215, Aug. 1998.
-
(1998)
IEEE Trans. Comp., Packag., Manufact. Technol. B
, vol.21
, pp. 209-215
-
-
Chen, H.H.1
Neely, J.S.2
-
6
-
-
0025594168
-
Global routing based on steiner min-max tree
-
Dec.
-
C. Chiang and M. Sarrafzadeh, "Global routing based on steiner min-max tree," IEEE Trans. Computer-Aided Design, vol. 9, pp. 1318-1325, Dec. 1990.
-
(1990)
IEEE Trans. Computer-aided Design
, vol.9
, pp. 1318-1325
-
-
Chiang, C.1
Sarrafzadeh, M.2
-
7
-
-
0032315113
-
Noise considerations in circuit optimization
-
San Jose, CA, Nov.
-
A. R. Conn, R. A. Haring, and C. Visweswariah, "Noise considerations in circuit optimization," in Proc. Int. Conf. Computer-Aided Design, San Jose, CA, Nov. 1998, pp. 220-227.
-
(1998)
Proc. Int. Conf. Computer-aided Design
, pp. 220-227
-
-
Conn, A.R.1
Haring, R.A.2
Visweswariah, C.3
-
8
-
-
0000208736
-
The generalized adjoint network and network sensitivities
-
Aug.
-
S. W. Director and R. A. Rohrer, "The generalized adjoint network and network sensitivities," IEEE Trans. Circuit Theory, vol. 16, pp. 318-323, Aug. 1969.
-
(1969)
IEEE Trans. Circuit Theory
, vol.16
, pp. 318-323
-
-
Director, S.W.1
Rohrer, R.A.2
-
9
-
-
0026108052
-
Sensitivity computation in piecewise approximation circuit simulation
-
Feb.
-
P. Feldmann, T. V. Nguyen, S. W. Director, and R. A. Rohrer, "Sensitivity computation in piecewise approximation circuit simulation," IEEE Trans. Computer-Aided Design, vol. 10, pp. 171-183, Feb. 1991.
-
(1991)
IEEE Trans. Computer-aided Design
, vol.10
, pp. 171-183
-
-
Feldmann, P.1
Nguyen, T.V.2
Director, S.W.3
Rohrer, R.A.4
-
10
-
-
0003468941
-
-
Stanford, CA: Dept. Oper. Res., Stanford Univ., July
-
P. E. Gill, W. Murray, M. A. Saunders, and M. H. Wright, User's Guide for SOL/QPSOL: A Fortran Package for Quadratic Programming. Stanford, CA: Dept. Oper. Res., Stanford Univ., July 1983.
-
(1983)
User's Guide for SOL/QPSOL: A Fortran Package for Quadratic Programming
-
-
Gill, P.E.1
Murray, W.2
Saunders, M.A.3
Wright, M.H.4
-
11
-
-
0034478158
-
A timing-constrained algorithm for simultaneous routing of multiple nets
-
San Jose, CA
-
J. Hu and S. S. Sapatnekar, "A timing-constrained algorithm for simultaneous routing of multiple nets," in Proc. Int. Conf. Computer-Aided Design, San Jose, CA, 2000, pp. 99-103.
-
(2000)
Proc. Int. Conf. Computer-aided Design
, pp. 99-103
-
-
Hu, J.1
Sapatnekar, S.S.2
-
12
-
-
0033683771
-
Fast power grid simulation
-
Los Angeles, CA, June
-
J. N. Kozhaya, S. R. Nassif, and F. N. Najm, "Fast power grid simulation," in Proc. Design Automation Conf., Los Angeles, CA, June 2000, pp. 156-161.
-
(2000)
Proc. Design Automation Conf.
, pp. 156-161
-
-
Kozhaya, J.N.1
Nassif, S.R.2
Najm, F.N.3
-
13
-
-
0035788945
-
Simultaneous signal and power routing under Keff model
-
Sonoma, CA
-
J. D. Z. Ma and L. He, "Simultaneous signal and power routing under Keff model," in Proc. Int. Workshop Syst. -Level Interconnect Prediction, Sonoma, CA, 2001, pp. 175-182.
-
(2001)
Proc. Int. Workshop Syst. -level Interconnect Prediction
, pp. 175-182
-
-
Ma, J.D.Z.1
He, L.2
-
14
-
-
0036051062
-
Toward global routing with RLC crosstalk constraints
-
New Orleans, LA
-
_, "Toward global routing with RLC crosstalk constraints," in Proc. Design Automation Conf., New Orleans, LA, 2002, pp. 669-672.
-
(2002)
Proc. Design Automation Conf.
, pp. 669-672
-
-
-
15
-
-
0027004894
-
Power and ground network topology optimization for cell-based VLSIs
-
Anaheim, CA. June
-
T. Mitsuhashi and E. S. Kuh, "Power and ground network topology optimization for cell-based VLSIs," in Proc. Design Automation Conf., Anaheim, CA. June 1992, pp. 524-529.
-
(1992)
Proc. Design Automation Conf.
, pp. 524-529
-
-
Mitsuhashi, T.1
Kuh, E.S.2
-
16
-
-
0023313404
-
A simple yet effective technique for global wiring
-
Mar.
-
R. Nair, "A simple yet effective technique for global wiring," IEEE Trans. Computer-Aided Design, vol. 6, pp. 165-172, Mar. 1987.
-
(1987)
IEEE Trans. Computer-aided Design
, vol.6
, pp. 165-172
-
-
Nair, R.1
-
17
-
-
0033683771
-
Fast power grid simulation
-
Los Angeles, CA, June
-
S. R. Nassif and J. N. Kozhaya, "Fast power grid simulation," in Proc. Design Automation Conf., Los Angeles, CA, June 2000, pp. 156-161.
-
(2000)
Proc. Design Automation Conf.
, pp. 156-161
-
-
Nassif, S.R.1
Kozhaya, J.N.2
-
20
-
-
0023314914
-
A global router based on a multicommodity flow model
-
E. Shragowitz and S. Keel, "A global router based on a multicommodity flow model," Integration: VLSI J., vol. 5, no. 1, pp. 3-16, 1987.
-
(1987)
Integration: VLSI J.
, vol.5
, Issue.1
, pp. 3-16
-
-
Shragowitz, E.1
Keel, S.2
-
21
-
-
0034483875
-
Fast analysis and optimization of power/ground networks
-
San Jose, CA, Nov.
-
H. Su, K. H. Gala, and S. S. Sapatnekar, "Fast analysis and optimization of power/ground networks," in Proc. Int. Conf. Computer-Aided Design, San Jose, CA, Nov. 2000, pp. 477-480.
-
(2000)
Proc. Int. Conf. Computer-aided Design
, pp. 477-480
-
-
Su, H.1
Gala, K.H.2
Sapatnekar, S.S.3
-
22
-
-
0036374252
-
An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts
-
San Diego, CA
-
H. Su. S. S. Sapatnekar, and S. R. Nassif, "An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts," in Proc. Int. Symp. Phys. Design, San Diego, CA, 2002, pp. 68-73.
-
(2002)
Proc. Int. Symp. Phys. Design
, pp. 68-73
-
-
Su, H.1
Sapatnekar, S.S.2
Nassif, S.R.3
-
23
-
-
0032643254
-
Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings
-
New Orleans. LA, June
-
X. Tan, C. J. R. Shi, D. Lungeanu, J. Lee, and L. Yuan, "Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings," in Proc. Design Automation Conf., New Orleans. LA, June 1999, pp. 156-161.
-
(1999)
Proc. Design Automation Conf.
, pp. 156-161
-
-
Tan, X.1
Shi, C.J.R.2
Lungeanu, D.3
Lee, J.4
Yuan, L.5
-
24
-
-
0020833410
-
Routing and techniques for gate array
-
Oct.
-
B. S. Ting and B. N. Tien, "Routing and techniques for gate array," IEEE Trans. Computer-Aided Design, vol. 2, pp. 301-312, Oct. 1983.
-
(1983)
IEEE Trans. Computer-aided Design
, vol.2
, pp. 301-312
-
-
Ting, B.S.1
Tien, B.N.2
-
25
-
-
0041589384
-
On-chip power supply network optimization using multigrid-based technique
-
Los Angeles, CA, June
-
K. Wang and M. Marek-Sadowska, "On-chip power supply network optimization using multigrid-based technique," in Proc. Design Automation Conf., Los Angeles, CA, June 2003. pp. 113-118.
-
(2003)
Proc. Design Automation Conf.
, pp. 113-118
-
-
Wang, K.1
Marek-Sadowska, M.2
-
26
-
-
0035212912
-
Area minimization of power distribution network using efficient nonlinear programming techniques
-
San Jose, CA
-
X. Wu, X. Hong, Y. Cai, C. K. Cheng, J. Gu, and W. Dai, "Area minimization of power distribution network using efficient nonlinear programming techniques," in Proc. Int. Conf. Computer-Aided Design, San Jose, CA, 2001, pp. 153-157.
-
(2001)
Proc. Int. Conf. Computer-aided Design
, pp. 153-157
-
-
Wu, X.1
Hong, X.2
Cai, Y.3
Cheng, C.K.4
Gu, J.5
Dai, W.6
-
27
-
-
0033720566
-
Hierarchical analysis of power distribution networks
-
Los Angeles, CA, June
-
M. Zhao, R. V. Panda, S. S. Sapatnekar, T. Edwards, R. Chaudhry, and D. Blaauw, "Hierarchical analysis of power distribution networks," in Proc. Design Automation Conf., Los Angeles, CA, June 2000, pp. 481-486.
-
(2000)
Proc. Design Automation Conf.
, pp. 481-486
-
-
Zhao, M.1
Panda, R.V.2
Sapatnekar, S.S.3
Edwards, T.4
Chaudhry, R.5
Blaauw, D.6
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