Synthesizing a representative critical path for post-silicon delay prediction

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 2009, Pages 183-190

  Liu, Qunzeng ^a   Sapatnekar, Sachin S ^a  

^a UNIVERSITY OF MINNESOTA   (United States)

Author keywords

Post silicon optimization; Representative critical path

Indexed keywords

AVERAGE PREDICTION ERROR; CIRCUIT DELAYS; CRITICAL PATHS; GUARD BANDS; GUARD-BAND; HIGHLY-CORRELATED; NOVEL ALGORITHM; NUMBER OF SAMPLES; POST-SILICON; POST-SILICON OPTIMIZATION; REPLICA METHOD; REPRESENTATIVE CRITICAL PATH; WORST CASE;

ALGORITHMS; DELAY CIRCUITS;

INTEGRATED CIRCUIT TESTING;

EID: 70349089251     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1514932.1514973     Document Type: Conference Paper

References (21)

1. H. Chang and S. S. Sapatnekar, "Statistical Timing Analysis Considering Spatial Correlations using a Single PERT-Like Traversal," in Proceedings of the IEEE/ACM International Conference on Computer Aided Design, pp. 621-625, Nov. 2003.
2. C. Visweswariah, K. Ravindran, K. Kalafala, S. G. Walker, and S. Narayan, "First-Order Incremental Block-Based Statistical Timing Analysis," in Proceedings of the ACM/IEEE Design Automation Conference, pp. 331-336, June 2004.
3. Y. Zhan, A. J. Strojwas, X. Li, L. Pileggi, D. Newmark, and M. Sharma, "Correlation-Aware Statistical Timing Analysis with Non-Gaussian Delay Distributions," in Proceedings of the ACM/IEEE Design Automation Conference, pp. 77-82, June 2005.
4. J. Le, X. Li, and L. Pileggi, "STAC: Statistical Timing Analysis with Correlation," in Proceedings of the ACM/IEEE Design Automation Conference, pp. 343-348, June 2004.
5. A. Agarwal, D. Blaauw, V. Zolotov, and S. Vrudhula, "Statistical Timing Analysis Using Bounds and Selective Enumeration," in Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, pp. 29-36, Dec. 2002.
6. A. Devgan and C. Kashyap, "Block-based Static Timing Analysis with Uncertainty," in Proceedings of the IEEE/ACM International Conference on Computer Aided Design, pp. 607-614, Nov. 2003.
7. B. Lee, L. Wang, and M. S. Abadir, "Refined Statistical Static Timing Analysis Through Learning Spatial Delay Correlations," in Proceedings of the ACM/IEEE Design Automation Conference, pp. 149-154, July 2006.
8. L. Wang, P. Bastani, and M. S. Abadir, "Design-Silicon Timing Correlation-A Data Mining Perspective," in Proceedings of the ACM/IEEE Design Automation Conference, pp. 385-389, June 2007.
9. A. Davoodi and A. Srivastava, "Variability Driven Gate Sizing for Binning Yield Optimization," in Proceedings of the ACM/IEEE Design Automation Conference, pp. 956-964, July 2006.
10. V. Khandelwal and A. Srivastava, "Variability-Driven Formulation for Simultaneous Gate Sizing and Postsilicon Tunability Allocation," in Proceedings of the International Symposium on Physical Design, pp. 11-18, Mar. 2007.
11. M. Abranmovici, P. Bradley, K. Dwarakanath, P. Levin, G. Memmi, and D. Miller, "A Reconfigurable Design-for-Debug Infrastructure for SoCs," in Proceedings of the ACM/IEEE Design Automation Conference, pp. 7-12, July 2006.
12. M. Mani, A. Singh, and M. Orshansky, "Joint Design-Time and Post-Silicon Minimization of Parametric Yield Loss using Adjustable Robust Optimization," in Proceedings of the IEEE/ACM International Conference on Computer Aided Design, pp. 19-26, Nov. 2006.
13. J. W. Tschanz, J. T. Kao, S. G. Narendra, R. Nair, D. A. Antoniadis, A. P. Chandrakasan, and V De, "Adaptive Body Bias for Reducing Impacts of Die-to-Die and Within-Die Parameter Variations on Microprocessor Frequency and Leakage," IEEE Journal of Solid-State Circuits, vol. 37, pp. 1396-1402, Nov. 2002.
14. J. W. Tschanz, S. Narendra, R. Nair, and V De, "Effectiveness of Adaptive Supply Voltage and Body Bias for Reducing the Impact of Parameter Variations in Low Power and High Performance Microprocessors," IEEE Journal of Solid-State Circuits, vol. 38, pp. 826-829, May 2003.
15. J. W. Tschanz, S. Narendra, A. Keshavarzi, and V. De, "Adaptive Circuit Techniques to Minimize Variation Impacts on Microprocessor Performance and Power," in Proceedings of the IEEE International Symposium on Circuits and Systems, pp. 23-26, May 2005.
16. Q. Liu and S. S. Sapatnekar, "Confidence Scalable Post-Silicon Statistical Delay Prediction under Process Variations," in Proceedings of the ACM/IEEE Design Automation Conference, pp. 492-502, June 2007.
17. M. Nakai, S. Akui, K. Seno, T. Meguro, T. Seki, T. Kondo, A. Hashiguchi, H. Kawahara, K. Kumano, and M. Shimura, "Dynamic Voltage and Frequency Management for a Low-Power Embedded Microprocessor," IEEE Journal of Solid-State Circuits, vol. 40, pp. 28-35, Nov. 2005.
18. M. Elgebaly and M. Sachdev, "Variation-A ware Adaptvie Voltage Scaling System," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 15, pp. 560-571, Nov. 2007.
19. H. Chang and S. S. Sapatnekar, "Statistical Timing Analysis Under Spatial Correlations," IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 24, pp. 1467-1482, Sept. 2005.
20. A. Caldwell, A. B. Kahng, and I. Markov, "Capo: a large-scale fixed-die placer," available at http://vlsicad.ucsd.edu/GSRC/bookshelf/ Slots/Placement.
21. A. Agarwal, D. Blaauw, V. Zolotov, S. Sundareswaran, M. Zhao, K. Gala, and R. Panda, "Path-Based Statistical Timing Analysis Considering Inter- and Intra-die Correlations," in Proceedings of the ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, pp. 16-21, Dec. 2002.