메뉴 건너뛰기




Volumn , Issue , 2005, Pages 309-314

An efficient algorithm for statistical minimization of total power under timing yield constraints

Author keywords

Leakage; Manufacturability; Statistical optimization

Indexed keywords

ALGORITHMS; BENCHMARKING; OPTIMIZATION; PROBABILITY DISTRIBUTIONS; PROBLEM SOLVING; STATISTICAL METHODS; THRESHOLD VOLTAGE;

EID: 27944441297     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/dac.2005.193823     Document Type: Conference Paper
Times cited : (97)

References (25)
  • 1
    • 0042635808 scopus 로고    scopus 로고
    • Death, taxes and failing chips
    • C. Visweswariah, "Death, taxes and failing chips," Proc. of DAC 2003, pp. 343-347.
    • (2003) Proc. of DAC , pp. 343-347
    • Visweswariah, C.1
  • 2
    • 0031122158 scopus 로고    scopus 로고
    • CMOS scaling into the nanometer regime
    • Y. Taur et al., "CMOS scaling into the nanometer regime," Proc. of the IEEE, no. 4, 1997, pp. 486-504.
    • (1997) Proc. of the IEEE , vol.4 , pp. 486-504
    • Taur, Y.1
  • 3
    • 0036916414 scopus 로고    scopus 로고
    • Methods for true power minimization
    • R. Brodersen et al., "Methods for True Power Minimization," in Proc. of ICCAD, 2002, pp. 35-40.
    • (2002) Proc. of ICCAD , pp. 35-40
    • Brodersen, R.1
  • 4
    • 0041633858 scopus 로고    scopus 로고
    • Parameter variation and impact on Circuits and Microarchitecture
    • S. Borkar et al., "Parameter variation and impact on Circuits and Microarchitecture," Proc. of DAC, 2003, pp. 338-342.
    • (2003) Proc. of DAC , pp. 338-342
    • Borkar, S.1
  • 5
    • 0032688692 scopus 로고    scopus 로고
    • Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing
    • S. Sirichotiyakul et al., "Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing," Proc. of DAC, 1999, pp. 436-441.
    • (1999) Proc. of DAC , pp. 436-441
    • Sirichotiyakul, S.1
  • 7
    • 1542359159 scopus 로고    scopus 로고
    • Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization
    • D. Nguyen et al., "Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization," Proc. of lSLPED, 2003, pp. 158-163.
    • (2003) Proc. of LSLPED , pp. 158-163
    • Nguyen, D.1
  • 8
    • 0346778721 scopus 로고    scopus 로고
    • Statistical timing analysis considering spatial correlations using a single PERT-like traversal
    • H. Chang and S. Sapatnekar, "Statistical timing analysis considering spatial correlations using a single PERT-like traversal," Proc. of ICCAD, 2003, pp. 621-625.
    • Proc. of ICCAD, 2003 , pp. 621-625
    • Chang, H.1    Sapatnekar, S.2
  • 9
    • 0036054545 scopus 로고    scopus 로고
    • Uncertainty aware circuit optimization
    • X. Bai et al., "Uncertainty aware circuit optimization," Proc. of DAC, 2002, pp. 58 - 63.
    • (2002) Proc. of DAC , pp. 58-63
    • Bai, X.1
  • 10
    • 85087239243 scopus 로고    scopus 로고
    • A methodology to improve timing yield
    • S. Raj et al., "A methodology to Improve Timing Yield," Proc. of DAC, 2004, pp. 448-453.
    • (2004) Proc. of DAC , pp. 448-453
    • Raj, S.1
  • 12
    • 27944447029 scopus 로고    scopus 로고
    • Gate sizing using a statistical delay model
    • E. Jacobs and M. Berkelaar, "Gate sizing using a statistical delay model," Proc. of DAC, 2000, pp. 283-290.
    • (2000) Proc. of DAC , pp. 283-290
    • Jacobs, E.1    Berkelaar, M.2
  • 13
    • 4444264520 scopus 로고    scopus 로고
    • Novel sizing algorithm for yield improvement under process variation in nanometer technology
    • June 7-11, 2004
    • P. Seung et al., "Novel sizing algorithm for yield improvement under process variation in nanometer technology", Proc. of DAC, 2004, June 7-11, 2004, pp. 454 - 459.
    • (2004) Proc. of DAC , pp. 454-459
    • Seung, P.1
  • 14
    • 17644377645 scopus 로고    scopus 로고
    • A new statistical optimization algorithm for gate sizing
    • M. Mani and M. Orshansky, "A new statistical optimization algorithm for gate sizing," Proc. of lCCD, 2004, pp. 272 - 277.
    • (2004) Proc. of LCCD , pp. 272-277
    • Mani, M.1    Orshansky, M.2
  • 15
    • 0022231945 scopus 로고
    • TILOS: A posynomial programming approach to transistor sizing
    • J. Fishburn and A. Dunlop, "TILOS: A Posynomial Programming Approach to Transistor Sizing," Proc. of ICCAD, 1985, pp. 326-328.
    • (1985) Proc. of ICCAD , pp. 326-328
    • Fishburn, J.1    Dunlop, A.2
  • 16
    • 3843068759 scopus 로고    scopus 로고
    • Methods for true energy-performance optimization
    • D. Markovic et al., "Methods for true energy-performance optimization," J. of Solid-Stale Circuits, 2004, pp. 1282- 1293.
    • (2004) J. of Solid-stale Circuits , pp. 1282-1293
    • Markovic, D.1
  • 17
    • 0036575359 scopus 로고    scopus 로고
    • Fast and exact transistor sizing based on iterative relaxation
    • V. Sundararajan et al., "Fast and Exact Transistor sizing Based on Iterative Relaxation," IEEE Trans, on CAD, vol. 21, 2002, pp.568-581.
    • (2002) IEEE Trans, on CAD , vol.21 , pp. 568-581
    • Sundararajan, V.1
  • 18
    • 0036907029 scopus 로고    scopus 로고
    • Subthreshold leakage modeling and reduction techniques
    • J. Kao et al. "Subthreshold Leakage Modeling and Reduction Techniques," Proc. of ICCAD, 2002, pp. 141-149.
    • (2002) Proc. of ICCAD , pp. 141-149
    • Kao, J.1
  • 23
    • 84888900952 scopus 로고    scopus 로고
    • http://www.mosek.com/documentation.html#manuals
  • 24
    • 0033712799 scopus 로고    scopus 로고
    • New paradigm of predictive MOSFET and interconnect modeling for early circuit design
    • Y. Cao et al., "New paradigm of predictive MOSFET and interconnect modeling for early circuit design," Proc. of IEEE CICC, 2000, pp. 201-204.
    • (2000) Proc. of IEEE CICC , pp. 201-204
    • Cao, Y.1
  • 25
    • 0024754187 scopus 로고
    • Matching properties of MOS transistors
    • M. Pelgrom et al. Matching Properties of MOS Transistors, IEEE Journal of Solid-State Circuits, vol. 24, 1989, pp. 1433-1440.
    • (1989) IEEE Journal of Solid-state Circuits , vol.24 , pp. 1433-1440
    • Pelgrom, M.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.