Stress-driven 3D-IC placement with TSV keep-out zone and regularity study

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2010, Pages 669-674

  Athikulwongse, Krit ^a   Chakraborty, Ashutosh ^b   Yangt, Jae Seok ^b   Pan, David Z ^b   Lim, Sung Kyu ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b The University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; ELECTRONICS PACKAGING; HALL MOBILITY; HOLE MOBILITY; TIMING CIRCUITS;

3-D INTEGRATION; 3-D PLACEMENTS; DRIVEN FORCE; INDUCED STRESS; KEEP-OUT-ZONE; MOBILITY VARIATION; STRESS-INDUCED; THROUGH-SILICON-VIA (TSV);

THREE DIMENSIONAL INTEGRATED CIRCUITS;

EID: 78650859591     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2010.5654245     Document Type: Conference Paper

References (11)

1. D. H. Kim, K. Athikulwongse, and S. K. Lim, "A. study of throughsilicon-via impact on the 3D stacked IC layout," in Proc. IEEE Int. Conf. Computer-Aided Design, San Jose, CA, Nov. 2-5 2009, pp. 674-680.
2. T. Dao, D. H. Triyoso, M. Petras, and M. Canonico, "Through silicon via stress characterization," in Proc. IEEE Int. Conf. on Integrated Circuit Design and Technology, Austin, TX, May 18-20 2009, pp. 39-41.
3. K. H. Lu. et al., "Thermo-mechanical reliability of 3-D ICs containing through silicon vias," in IEEE Electronic Components and Technology Conf., San Diego, CA, May 26-29 2009, pp. 630-634.
4. C. S. Selvanayagam et al., "Nonlinear thermal stress/strain analyses of copper filled TSV (through silicon via) and their flip-chip microbumps," in IEEE Electronic Components and Technology Conf, Lake Buena Vista, FL, May 27-30 2008, pp. 1073-1081.
5. C. Okoro et al., "Analysis of the induced stresses in silicon during thermcompression Cu-Cu bonding of Cu-through-vias in 3D-SIC architecture," in IEEE Electronic Components and Technology Conf, Reno, NV, May 29-June 1 2007, pp. 249-255.
6. S. E. Thompson et al., "A. 90-nm logic technology featuring strainedsilicon," IEEE Trans. on Electron Devices, vol. 51, no. 11, pp. 1790-1797, Nov. 2004.
7. A. B. Kahng, P. Sharma, and. R. O. Topaloglu, "Exploiting STI stress for performance," in Proc. IEEE Int. Conf. Computer-Aided Design, San Jose, CA, Nov. 5-8 2007, pp. 83-90.
8. A. Chakraborty, S. X. Shi, and D. Z. Pan, "Layout level timing optimization by leveraging active area dependent mobility of strainedsilicon devices," in Proc. Design, Automation and Test in Europe, Munich, Germany, Mar. 10-14 2008, pp. 849-855.
9. J.-S. Yang, K. Athikulwongse, Y-J. Lee, S. K. Lim, and D. Z. Pan, "TSV stress aware timing analysis with applications to 3D-IC layout optimization," in Proc. ACM Design Automation Conf., Anaheim, CA, June 13-18 2010, pp. 803-806.
10. P. Spindler, U. Schlichtmann, and F. M. Johannes, "Kraftwerk2-A fast force-directed quadratic placement approach using an accurate net model," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 8, pp. 1398-1411, Aug. 2008.
11. IWLS. (2005, June) IWLS 2005 benchmarks. [Online]. Available: http://www.iwls.org/iwls2005/benchmarks.html