-
1
-
-
0028583468
-
Comparison of methods of computing correlated lognormal sum distributions and outages for digital wireless applications
-
A. A. Abu-Dayya and N. C. Beaulieu, "Comparison of methods of computing correlated lognormal sum distributions and outages for digital wireless applications," IEEE 44th Vehicular Technology Conference, vol. 1, pp. 175-179, 1994.
-
(1994)
IEEE 44th Vehicular Technology Conference
, vol.1
, pp. 175-179
-
-
Abu-Dayya, A.A.1
Beaulieu, N.C.2
-
2
-
-
0035424789
-
A circuit level perspective of the optimum gate oxide thickness
-
K. A. Bowman, L. Wang, X. Tang and J. D. Meindl, "A Circuit Level Perspective of the Optimum Gate Oxide Thickness," IEEE Transction on Electron Devices, pp. 1800-1810, 2001.
-
(2001)
IEEE Transction on Electron Devices
, pp. 1800-1810
-
-
Bowman, K.A.1
Wang, L.2
Tang, X.3
Meindl, J.D.4
-
3
-
-
0346778721
-
Statistical timing analysis considering spatial correlations using a single PERT-like traversal
-
H. Chang and S. S. Sapatnekar, "Statistical Timing Analysis Considering Spatial Correlations Using a Single PERT-like Traversal," International Conference on Computer Aided Design, pp. 621-625, 2003.
-
(2003)
International Conference on Computer Aided Design
, pp. 621-625
-
-
Chang, H.1
Sapatnekar, S.S.2
-
4
-
-
0036907253
-
Standby power optimization via transistor sizing and dual threshold voltage assignment
-
M. Ketkar and S. S. Sapatnekar", "Standby Power Optimization via Transistor Sizing and Dual Threshold Voltage Assignment," International Conference on Computer-Aided Design, pp. 375-378, 2002.
-
(2002)
International Conference on Computer-aided Design
, pp. 375-378
-
-
Ketkar, M.1
Sapatnekar, S.S.2
-
5
-
-
0041589378
-
Analysis and minimization techniques for total leakage considering gate oxide leakage
-
D. Lee, W. Kwong, D. Blaauw and D. Sylvester, "Analysis and Minimization Techniques for Total Leakage Considering Gate Oxide Leakage," Design Automation Conference, pp. 175-180, 2003.
-
(2003)
Design Automation Conference
, pp. 175-180
-
-
Lee, D.1
Kwong, W.2
Blaauw, D.3
Sylvester, D.4
-
6
-
-
1542329235
-
Modeling and estimation of total leakage current in nano-scaled CMOS devices considering the effect of parameter variation
-
S. Mukhopadhyay and K. Roy, "Modeling and Estimation of Total Leakage Current in Nano-scaled CMOS Devices Considering the Effect of Parameter Variation," International Symposium on Low Power Electronics and Design, pp. 172-175, 2003.
-
(2003)
International Symposium on Low Power Electronics and Design
, pp. 172-175
-
-
Mukhopadhyay, S.1
Roy, K.2
-
7
-
-
0036949325
-
Full-chip sub-threshold leakage power prediction model for sub-0.18um CMOS
-
S. Narendra, V. De, S. Borkar, D. Antoniadis and A. Chandrakasan, "Full-chip sub-threshold leakage power prediction model for sub-0.18um CMOS," International Symposium on Low Power Electronics and Design, pp. 19-23, 2002.
-
(2002)
International Symposium on Low Power Electronics and Design
, pp. 19-23
-
-
Narendra, S.1
De, V.2
Borkar, S.3
Antoniadis, D.4
Chandrakasan, A.5
-
9
-
-
4444351567
-
Parametric yield estimation considering leakage variability
-
R. Rao, A. Devgan, D. Blaauw and D. Sylvester, "Parametric yield estimation considering leakage variability," Design Automation Conference, pp. 442-447, 2003
-
(2003)
Design Automation Conference
, pp. 442-447
-
-
Rao, R.1
Devgan, A.2
Blaauw, D.3
Sylvester, D.4
-
10
-
-
1542269365
-
Statistical estimation of leakage current considering inter- And intra-die process variation
-
R. Rao, A. Srivastava, D. Blaauw and D. Sylvester, "Statistical Estimation of Leakage Current Considering Inter- and Intra-Die Process Variation," International Symposium on Low Power Electronics and Design, pp. 19-23, 2003.
-
(2003)
International Symposium on Low Power Electronics and Design
, pp. 19-23
-
-
Rao, R.1
Srivastava, A.2
Blaauw, D.3
Sylvester, D.4
-
11
-
-
0032688692
-
Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing
-
S. Sirichotiyakul, T. Edwards, C. Oh, J. Zuo, A. Dharchoudhury, R. Panda and D. Blaauw, "Stand-by power minimization through simultaneous threshold voltage selection and circuit sizing," Design Automation Conference, pp. 436-441, 1999.
-
(1999)
Design Automation Conference
, pp. 436-441
-
-
Sirichotiyakul, S.1
Edwards, T.2
Oh, C.3
Zuo, J.4
Dharchoudhury, A.5
Panda, R.6
Blaauw, D.7
-
12
-
-
0036954781
-
Modeling and analysis of leakage power considering within-die process variations
-
A. Srivastava, R. Bai, D. Blaauw and D. Sylvester, "Modeling and analysis of leakage power considering within-die process variations," International Symposium on Low Power Electronics and Design, pp. 64-67, 2002.
-
(2002)
International Symposium on Low Power Electronics and Design
, pp. 64-67
-
-
Srivastava, A.1
Bai, R.2
Blaauw, D.3
Sylvester, D.4
-
13
-
-
4444319095
-
Tradeoffs between gate oxide leakage and delay for dual tox circuits
-
A. Sultania, D. Sylvester, and S. S. Sapamekar, "Tradeoffs between Gate Oxide Leakage and Delay for Dual Tox Circuits," Design Automation Conference, pp. 761-766, 2004.
-
(2004)
Design Automation Conference
, pp. 761-766
-
-
Sultania, A.1
Sylvester, D.2
Sapamekar, S.S.3
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