LEAP: Layout design through error-aware transistor positioning for soft-error resilient sequential cell design

IEEE International Reliability Physics Symposium Proceedings

Volumn , Issue , 2010, Pages 203-212

  Lee, Hsiao Heng Kelin ^a   Lilja, Klas ^c   Bounasser, Mounaim ^c   Relangi, Prasanthi ^a   Linscott, Ivan R ^a   Inan, Umran S ^a   Mitra, Subhasish ^b  

^a Department of Electrical Engineering ^*  (South Korea)

^b Stanford University   (United States)

^c Robust Chip Inc   (United States)

Author keywords

Dual interlocked storage cell (DICE); Flip flop; Layout; LEAP; Multiple bit upset (MBU) latch; Proton irradiation; Single event multiple upset (SEMU); Single event upset (SEU); Soft error

Indexed keywords

DUAL INTERLOCKED STORAGE CELLS; FLIP-FLOP; LAYOUT; LEAP; MULTIPLE BIT UPSET; SINGLE EVENT UPSETS; SINGLE-EVENT MULTIPLE-UPSET; SOFT ERROR;

DESIGN; DIGITAL INTEGRATED CIRCUITS; ELECTRIC NETWORK TOPOLOGY; ERRORS; PROTON IRRADIATION; PROTONS; STATIC RANDOM ACCESS STORAGE;

FLIP FLOP CIRCUITS;

EID: 77957911501     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IRPS.2010.5488829     Document Type: Conference Paper

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