Confidence scalable post-silicon statistical delay prediction under process variations

Proceedings - Design Automation Conference

Volumn , Issue , 2007, Pages 497-502

  Qunzeng, Liu ^a   Sapatnekar, Sachin S ^a  

^a UNIVERSITY OF MINNESOTA   (United States)

Author keywords

Post silicon optimization; Statistical timing analysis

Indexed keywords

POST-SILICON OPTIMIZATION; PROCESS VARIATIONS; STANDARD DEVIATION; STATISTICAL TIMING ANALYSIS;

CHIP SCALE PACKAGES; ELECTRIC NETWORK ANALYSIS; PARAMETER ESTIMATION; STATISTICAL METHODS;

INTEGRATED CIRCUIT TESTING;

EID: 34547322816     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.2007.375216     Document Type: Conference Paper

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