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Volumn 2005, Issue , 2005, Pages 1023-1028

Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL METHODS; CORRELATION METHODS; INFORMATION RETRIEVAL; LEAKAGE CURRENTS; OPTIMIZATION; STATISTICAL METHODS;

EID: 33751414776     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2005.1560212     Document Type: Conference Paper
Times cited : (61)

References (24)
  • 1
    • 0036911849 scopus 로고    scopus 로고
    • Sub-90 nm technologies challenges and opportunities for CAD
    • T. Karnik, S. Borkar, and V. De, "Sub-90 nm technologies challenges and opportunities for CAD," ACM/IEEE ICCAD, pp. 203-206, 2002.
    • (2002) ACM/IEEE ICCAD , pp. 203-206
    • Karnik, T.1    Borkar, S.2    De, V.3
  • 2
    • 84886705903 scopus 로고    scopus 로고
    • Parametric yield analysis and constrained-based supply voltage optimization
    • R. Rao et al., "Parametric yield analysis and constrained-based supply voltage optimization," ACM/IEEE ISQED, pp. 284-290, 2005.
    • (2005) ACM/IEEE ISQED , pp. 284-290
    • Rao, R.1
  • 3
    • 0346778721 scopus 로고    scopus 로고
    • Statistical timing analysis considering spatial correlations using a single PERT-like traversal
    • H. Chang and S. S. Sapatnekar, "Statistical timing analysis considering spatial correlations using a single PERT-like traversal," ACM/IEEE ICCAD, pp. 621-625, 2003.
    • (2003) ACM/IEEE ICCAD , pp. 621-625
    • Chang, H.1    Sapatnekar, S.S.2
  • 4
    • 4444233012 scopus 로고    scopus 로고
    • First-order incremental block-based statistical timing analysis
    • C. Viswesweriah et al., "First-order incremental block-based statistical timing analysis," ACM/IEEE DAC, pp. 331-336, 2004.
    • (2004) ACM/IEEE DAC , pp. 331-336
    • Viswesweriah, C.1
  • 5
    • 0141852377 scopus 로고    scopus 로고
    • Statistical timing analysis using bounds and selective enumeration
    • pp. 1243-1260, Sept.
    • A. Agarwal et al., "Statistical timing analysis using bounds and selective enumeration," IEEE Trans. on CAD, pp. 1243-1260, pp. 1243-1260, Sept. 2003.
    • (2003) IEEE Trans. on CAD , pp. 1243-1260
    • Agarwal, A.1
  • 6
    • 0348040110 scopus 로고    scopus 로고
    • Block-based statistical timing analysis with uncertainty
    • A. Devgan and C. Kashyap, "Block-Based statistical timing analysis with uncertainty," ACM/IEEE ICCAD, pp. 607-614, 2003.
    • (2003) ACM/IEEE ICCAD , pp. 607-614
    • Devgan, A.1    Kashyap, C.2
  • 7
    • 4444323973 scopus 로고    scopus 로고
    • Fast statistical timing analysis handling arbitrary delay correlations
    • M. Orshansky and A. Bandopadhyay, "Fast statistical timing analysis handling arbitrary delay correlations," ACM/IEEE DAC, pp. 337-342, 2004.
    • (2004) ACM/IEEE DAC , pp. 337-342
    • Orshansky, M.1    Bandopadhyay, A.2
  • 8
    • 1642276264 scopus 로고    scopus 로고
    • Statistical analysis of subthreshold leakage current for VLSI circuits
    • Feb.
    • R.R. Rao, et al., "Statistical analysis of subthreshold leakage current for VLSI circuits," IEEE Trans. VLSI Systems, pp. 131-139, Feb. 2004.
    • (2004) IEEE Trans. VLSI Systems , pp. 131-139
    • Rao, R.R.1
  • 9
    • 0036949325 scopus 로고    scopus 로고
    • Full-chip sub-threshold leakage power prediction model for sub-0.18μm CMOS
    • S. Narendra et al., "Full-chip sub-threshold leakage power prediction model for sub-0.18μm CMOS," ACM/IEEE ISLPED, pp. 19-23, 2002.
    • (2002) ACM/IEEE ISLPED , pp. 19-23
    • Narendra, S.1
  • 10
    • 0036054545 scopus 로고    scopus 로고
    • Uncertainty aware circuit optimization
    • X. Bai, et al., "Uncertainty aware circuit optimization," ACM/IEEE DAC, pp.58-63, 2002.
    • (2002) ACM/IEEE DAC , pp. 58-63
    • Bai, X.1
  • 11
    • 4444333242 scopus 로고    scopus 로고
    • A methodology to improve timing yield in the presence of process variations
    • S. Raj, S. Vrudhula, and J. Wang, "A methodology to improve timing yield in the presence of process variations," ACM/IEEE DAC, pp. 448-453, 2004.
    • (2004) ACM/IEEE DAC , pp. 448-453
    • Raj, S.1    Vrudhula, S.2    Wang, J.3
  • 12
    • 4444264520 scopus 로고    scopus 로고
    • Novel sizing algorithm for yield improvement under process variation in nanometer technology
    • S. Choi, B. Paul and K. Roy, "Novel sizing algorithm for yield improvement under process variation in nanometer technology," IEEE/ACMDAC, pp. 454-459, 2004.
    • (2004) IEEE/ACMDAC , pp. 454-459
    • Choi, S.1    Paul, B.2    Roy, K.3
  • 13
    • 33646928098 scopus 로고    scopus 로고
    • Statistical timing based optimization using gate sizing
    • A. Agarwal et al., "Statistical timing based optimization using gate sizing," ACM/IEEE DATE, pp. 400-405, 2005.
    • (2005) ACM/IEEE DATE , pp. 400-405
    • Agarwal, A.1
  • 14
    • 4444277442 scopus 로고    scopus 로고
    • Statistical optimization of leakage power considering process variations using dual-Vth and sizing
    • A. Srivastava, D. Sylvester, and D. Blaauw, "Statistical optimization of leakage power considering process variations using dual-Vth and sizing," ACM/IEEE DAC, pp. 773-778, 2004.
    • (2004) ACM/IEEE DAC , pp. 773-778
    • Srivastava, A.1    Sylvester, D.2    Blaauw, D.3
  • 15
    • 16244380812 scopus 로고    scopus 로고
    • Variability inspired implementation selection problem
    • A. Davoodi, V. Khandelwal, and A. Srivastava, "Variability inspired implementation selection problem," ACM/IEEE ICCAD, pp. 423-427, 2004.
    • (2004) ACM/IEEE ICCAD , pp. 423-427
    • Davoodi, A.1    Khandelwal, V.2    Srivastava, A.3
  • 16
    • 17644377645 scopus 로고    scopus 로고
    • A new statistical algorithm for gate sizing
    • M. Mani and M. Orshansky, "A new statistical algorithm for gate sizing," ACM/IEEE ICCD, pp. 272-277, 2004.
    • (2004) ACM/IEEE ICCD , pp. 272-277
    • Mani, M.1    Orshansky, M.2
  • 17
    • 27944464454 scopus 로고    scopus 로고
    • Accurate and efficient gate level parametric yield estimation considering correlated variations in leakage power and performance
    • A. Srivastava et al., "Accurate and efficient gate level parametric yield estimation considering correlated variations in leakage power and performance," ACM/IEEE DAC, pp. 535-540, 2005..
    • (2005) ACM/IEEE DAC , pp. 535-540
    • Srivastava, A.1
  • 20
    • 0001310038 scopus 로고
    • The greatest of a finite set of random variables
    • C. Clark, "The greatest of a finite set of random variables," Operations Research, vol. 9, pp. 85-91, 1961.
    • (1961) Operations Research , vol.9 , pp. 85-91
    • Clark, C.1
  • 21
    • 0020180746 scopus 로고
    • On the distribution function and moments of power sums with lognormal components
    • Sep.
    • S.C. Schwartz and Y.S. Yeh, "On the distribution function and moments of power sums with lognormal components," Bell Systems Technical Journal, vol.61, pp.1441-1462, Sep. 1982.
    • (1982) Bell Systems Technical Journal , vol.61 , pp. 1441-1462
    • Schwartz, S.C.1    Yeh, Y.S.2
  • 22
    • 0041572425 scopus 로고
    • The bivariate normal integral
    • Dec.
    • J. H. Cadwell, "The bivariate normal integral," Biometrika, pp. 31-35, Dec. 1951.
    • (1951) Biometrika , pp. 31-35
    • Cadwell, J.H.1
  • 23
    • 0002609165 scopus 로고
    • A neutral netlist of 10 combinational benchmark circuits and a target translator in Fortran
    • May
    • F. Brglez and H. Fujiwara, "A neutral netlist of 10 combinational benchmark circuits and a target translator in Fortran," Proc. ISCAS, pp. 695-698, May 1989.
    • (1989) Proc. ISCAS , pp. 695-698
    • Brglez, F.1    Fujiwara, H.2
  • 24
    • 4444259541 scopus 로고    scopus 로고
    • Static timing analysis using backward propagation
    • D. Lee, V. Zolotov and D. Blaauw, "Static timing analysis using backward propagation," ACM/IEEE DAC, pp. 664-669, 2004.
    • (2004) ACM/IEEE DAC , pp. 664-669
    • Lee, D.1    Zolotov, V.2    Blaauw, D.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.