메뉴 건너뛰기




Volumn 2006, Issue , 2006, Pages 309-314

Temperature-aware routing in 3D ICs

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CONGESTION CONTROL (COMMUNICATION); ELECTRIC NETWORK ANALYSIS; HEAT RESISTANCE; INTEGRATED CIRCUITS; ITERATIVE METHODS; MICROPROCESSOR CHIPS; SENSITIVITY ANALYSIS;

EID: 33748589691     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1118299.1118377     Document Type: Conference Paper
Times cited : (91)

References (27)
  • 1
    • 33747566850 scopus 로고    scopus 로고
    • 3-D ICs: A novel chip design for improving deep submicrometer interconnect performance and system-on-chip integration
    • May
    • K. Banerjee, S. J. Souri, P. Kapur and K. C. Saraswat, "3-D ICs: A Novel Chip Design for Improving Deep Submicrometer Interconnect Performance and System-on-Chip Integration," Proc. of IEEE, 89(5), pp. 602-633, May 2001.
    • (2001) Proc. of IEEE , vol.89 , Issue.5 , pp. 602-633
    • Banerjee, K.1    Souri, S.J.2    Kapur, P.3    Saraswat, K.C.4
  • 2
    • 0034819419 scopus 로고    scopus 로고
    • Analysis and optimization of thermal issues in high-performance VLSI
    • K. Banerjee, M. Pedram and A. Ajami, "Analysis and Optimization of Thermal Issues in High-Performance VLSI," Proc. ISPD, 2001, pp. 230-237.
    • (2001) Proc. ISPD , pp. 230-237
    • Banerjee, K.1    Pedram, M.2    Ajami, A.3
  • 3
    • 0033871060 scopus 로고    scopus 로고
    • Cell-level placement for improving substrate thermal distribution
    • Feb.
    • C. H. Tsai and S. M. Kang, "Cell-Level Placement for Improving Substrate Thermal Distribution," IEEE Trans. CAD, 19(2), pp. 253-266, Feb. 2000.
    • (2000) IEEE Trans. CAD , vol.19 , Issue.2 , pp. 253-266
    • Tsai, C.H.1    Kang, S.M.2
  • 4
    • 16244394515 scopus 로고    scopus 로고
    • Efficient full-chip thermal modeling and analysis
    • P. Li, T. Pileggi, M. Asheghi and R. Chandra, "Efficient Full-Chip Thermal Modeling and Analysis," Proc. ICCAD, 2004, pp. 319-326.
    • (2004) Proc. ICCAD , pp. 319-326
    • Li, P.1    Pileggi, T.2    Asheghi, M.3    Chandra, R.4
  • 5
    • 0347409236 scopus 로고    scopus 로고
    • Efficient thermal placement of standard cells in 3D ICs using a force directed approach
    • B. Goplen and S. S. Sapatnekar, "Efficient Thermal Placement of Standard Cells in 3D ICs Using a Force Directed Approach," Proc. ICCAD, 2003, pp. 86-89.
    • (2003) Proc. ICCAD , pp. 86-89
    • Goplen, B.1    Sapatnekar, S.S.2
  • 6
    • 0033343885 scopus 로고    scopus 로고
    • An efficient method for hot-spot identification in ULSI circuits
    • Y. K. Cheng and S. M. Kang, "An Efficient Method for Hot-Spot Identification in ULSI Circuits," Proc. ICCAD, 1999, pp. 124-127.
    • (1999) Proc. ICCAD , pp. 124-127
    • Cheng, Y.K.1    Kang, S.M.2
  • 7
    • 84861418911 scopus 로고    scopus 로고
    • Fast computation of the temperature distribution in VLSI chips using the discrete cosine transform and table look-up
    • Y. Zhan and S.S. Sapatnekar, "Fast Computation of the Temperature Distribution in VLSI Chips Using the Discrete Cosine Transform and Table Look-up," Proc. ASP-DAC, 2005, pp. 87-92.
    • (2005) Proc. ASP-DAC , pp. 87-92
    • Zhan, Y.1    Sapatnekar, S.S.2
  • 8
    • 0026175670 scopus 로고
    • Routing the 3-D chip
    • R. J. Enbody and K. H. Tan, "Routing the 3-D Chip," Proc. DAC, 1992, pp. 132-137.
    • (1992) Proc. DAC , pp. 132-137
    • Enbody, R.J.1    Tan, K.H.2
  • 9
    • 0344982114 scopus 로고    scopus 로고
    • Physical design of the "2.5D" stacked system
    • Y. Deng and W. Maly, "Physical Design of the "2.5D" stacked System," Proc. ICCD, 2003, pp. 211-217.
    • (2003) Proc. ICCD , pp. 211-217
    • Deng, Y.1    Maly, W.2
  • 10
    • 28344456185 scopus 로고    scopus 로고
    • Three-dimensional place and route for FPGAs
    • C. Ababei, H. Morgal and K. Bazargan, "Three-dimensional Place and Route for FPGAs," Proc. ASP-DAC, 2005, pp. 773-778.
    • (2005) Proc. ASP-DAC , pp. 773-778
    • Ababei, C.1    Morgal, H.2    Bazargan, K.3
  • 11
    • 84954424983 scopus 로고    scopus 로고
    • Design tools for 3-D integrated Circuits
    • S. Das, A. Chandrakasan and R. Reif, "Design Tools for 3-D Integrated Circuits," Proc. ASP-DAC, 2003, pp. 53-56.
    • (2003) Proc. ASP-DAC , pp. 53-56
    • Das, S.1    Chandrakasan, A.2    Reif, R.3
  • 12
    • 84861422150 scopus 로고    scopus 로고
    • Thermal-driven multilevel routing for 3-D ICs
    • J. Cong and Y. Zhang, "Thermal-Driven Multilevel Routing for 3-D ICs," Proc. ASP-DAC, 2005, pp. 121-126.
    • (2005) Proc. ASP-DAC , pp. 121-126
    • Cong, J.1    Zhang, Y.2
  • 13
    • 0034452563 scopus 로고    scopus 로고
    • Effect of via separation and low-k dielectric materials on the thermal characteristics of Cu interconnects
    • T-Y Chiang, K. Banerjee and K. C. Saraswat, "Effect of Via Separation and Low-k Dielectric Materials on the Thermal Characteristics of Cu Interconnects," Tech. Dig. IEDM, 2000, pp. 261-264.
    • (2000) Tech. Dig. IEDM , pp. 261-264
    • Chiang, T.-Y.1    Banerjee, K.2    Saraswat, K.C.3
  • 14
    • 0035208728 scopus 로고    scopus 로고
    • Compact modeling and SPICE-based simulation for electrothermal analysis of multilevel ULSI interconnects
    • T-Y Chiang, K. Banerjee and K. C. Saraswat, "Compact Modeling and SPICE-Based Simulation for Electrothermal Analysis of Multilevel ULSI Interconnects," Proc. ICCAD, 2001, pp. 165-172.
    • (2001) Proc. ICCAD , pp. 165-172
    • Chiang, T.-Y.1    Banerjee, K.2    Saraswat, K.C.3
  • 15
    • 28344443452 scopus 로고    scopus 로고
    • Thermal via placement in 3D ICs
    • B. Goplen and S. S. Sapatnekar, "Thermal Via Placement in 3D ICs," Proc. ISPD, 2005, pp. 167-174.
    • (2005) Proc. ISPD , pp. 167-174
    • Goplen, B.1    Sapatnekar, S.S.2
  • 16
  • 17
    • 84859286129 scopus 로고    scopus 로고
    • http://www.tu-dresden.de/mwism/skalicky/laspack/laspack.html
  • 20
    • 0023313404 scopus 로고
    • A simple yet effective technique for global wiring
    • March
    • R. Nair, "A Simple Yet Effective Technique for Global Wiring," IEEE Trans. CAD, 6(2), pp. 165-172, March 1987.
    • (1987) IEEE Trans. CAD , vol.6 , Issue.2 , pp. 165-172
    • Nair, R.1
  • 21
  • 22
    • 0043092229 scopus 로고    scopus 로고
    • Improved global routing through congestion estimation
    • R. T. Hadsell and P. H. Madden, "Improved Global Routing through Congestion Estimation," Proc. DAC, 2003, pp. 28-34.
    • (2003) Proc. DAC , pp. 28-34
    • Hadsell, R.T.1    Madden, P.H.2
  • 23
    • 0001852170 scopus 로고    scopus 로고
    • An efficient implementation of a scaling minimum-cost low algorithm
    • A. V. Goldberg, "An Efficient Implementation of a Scaling Minimum-Cost low Algorithm",Journal of Algorithms, 22, pp. 1-29, 1997.
    • (1997) Journal of Algorithms , vol.22 , pp. 1-29
    • Goldberg, A.V.1
  • 24
    • 0029342313 scopus 로고
    • Prim-Dijkstra tradeoffs for improved performance-driven routing tree design
    • July
    • C.J. Alpert, T.C. Hu, J.H. Huang, A.B. Kahng and D. Karger, "Prim-Dijkstra Tradeoffs for Improved Performance-Driven Routing Tree Design," IEEE Trans. CAD, 14(7), pp. 890-896, July 1995.
    • (1995) IEEE Trans. CAD , vol.14 , Issue.7 , pp. 890-896
    • Alpert, C.J.1    Hu, T.C.2    Huang, J.H.3    Kahng, A.B.4    Karger, D.5
  • 25
    • 84859290494 scopus 로고    scopus 로고
    • http://groups.yahoo.com/group/lp.solve/
  • 26
    • 84859286125 scopus 로고    scopus 로고
    • http://www.cbl.ncsu.edu/pub/Benchmark_dirs/LayoutSynth92
  • 27
    • 84859293163 scopus 로고    scopus 로고
    • http://er.cs.ucla.edu/benchmarks/ibm-place/


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.