Current source modeling in the presence of body bias

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn , Issue , 2010, Pages 199-204

  Gupta, Saket ^a   Sapatnekar, Sachin S ^a  

^a UNIVERSITY OF MINNESOTA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

45NM TECHNOLOGY; ADAPTIVE BODY BIAS; BODY BIAS; CURRENT SOURCE MODELING; CURRENT SOURCES; HIGH-PERFORMANCE DESIGN; NEW APPROACHES; ORDERS OF MAGNITUDE; REDUCTION METHOD; SENSITIVITY METHODS; TIMING MODELS; WAVE FORMS; WORST-CASE ERRORS;

COMPUTER AIDED DESIGN; DIGITAL INTEGRATED CIRCUITS;

TIME MEASUREMENT;

EID: 77951217017     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASPDAC.2010.5419896     Document Type: Conference Paper

References (17)

1. 2, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme," in Proceedings of the IEEE International Solid- State Circuits Conference, pp. 166-167, 1996.
2. J. W. Tschanz, J. Kao, S. G. Narendra, R. Nair, D. Antoniadis, A. Chandrakasan, and V. De, "Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage," IEEE Journal of Solid-State Circuits, vol. 37, pp. 1396-1402, November 2002.
3. S. S. Sapatnekar, Timing. Boston, MA: Springer, 2004.
4. F. Dartu, N. Menezes, and L. Pileggi, "Performance computation for precharacterized CMOS gates with RC loads," IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 15, pp. 544-553, May 1996.
5. J. F. Croix and D. F. Wong, "Blade and Razor: Cell and interconnect delay analysis using current-based models," in Proceedings of the Design Automation Conference, pp. 386-389, 2003.
6. I. Keller, K. Tseng, and N. Verghese, "A robust cell-level crosstalk delay change analysis," in Proceedings of the International Conference on Computer-Aided Design, pp. 147-154, 2004.
7. P. Li and E. Acar, "A waveform independent gate model for accurate timing analysis," in Proceedings of the International Conference on Computer Design, pp. 363-365, 2005.
8. C. Amin, C. Kashyap, N. Menezes, K. Killpack, and E. Chiprout, "A multi-port current source model for multiple-input switching effects in CMOS library cells," in Proceedings of the Design Automation Conference, pp. 247-252, 2006.
9. N. Menezes, C. Kashyap, and C. Amin, "A "true" electrical cell model for timing, noise, and power grid verification," in Proceedings of the Design Automation Conference, pp. 462-467, 2008.
10. B. Amelifard, S. Hatami, H. Fatemi, and M. Pedram, "A current source model for CMOS logic cells considering multiple input switching and stack effect," in Proceedings of the Conference on Design, Automation and Test in Europe, pp. 568-573, 2008.
11. S. Raja, F. Varadi, M. Becer, and J. Geada, "Transistor level gate modeling for accurate and fast timing, noise, and power analysis," in Proceedings of the Design Automation Conference, pp. 456-461, 2008.
12. http://www.synopsys.com/products/mixedsignal/hspice/hspice.html.
13. J. F. Croix and D. F. Wong, "A fast and accurate technique to optimize characterization tables for logic synthesis," in Proceedings of the Design Automation Conference, pp. 337-340, 1997.
14. P. R. O'Brien and T. L. Savarino, "Modeling the driving point characteristic of resistive interconnect for accurate delay estimation," in Proceedings of the International Conference on Computer-Aided Design, pp. 512-515, 1989.
15. J. Tschanz, N. Kim, S. Dighe, J. Howard, G. Ruhl, S. Vanga, S. Narendra, Y. Hoskote, H. Wilson, C. Lam, M. Shuman, C. Tokunaga, D. Somasekhar, S. Tang, D. Finan, T. Karnik, N. Borkar, N. Kurd, and V. De, "Adaptive frequency and biasing techniques for tolerance to dynamic temperature-voltage variations and aging," in Proceedings of the IEEE International Solid-State Circuits Conference, pp. 292-604, 2007.
16. S. V. Kumar, C. H. Kim, and S. S. Sapatnekar, "Body bias voltage computations for process and temperature compensation," IEEE Transactions on Very Large Scale Integration Systems, vol. 16, pp. 249-262, March 2008.
17. Predictive Technology Model. http://www.eas.asu.edu/~ptm.