Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2006, Pages 204-209

  Choudhury, Mihir R ^a   Zhou, Quming ^a   Mohanram, Kartik ^a  

^a Rice University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATIONAL CIRCUITS; COMPUTER-AIDED DESIGN; DESIGN OPTIMIZATION (DO); DESIGN SPACE EXPLORATION (DSE); DUAL VDD; GEOMETRIC PROGRAMMING (GP); INTERNATIONAL CONFERENCES; OPTIMIZATION ALGORITHMS; OPTIMIZATION FRAMEWORK; POSYNOMIAL; POWER CONSTRAINTS; SIMULATION RESULTS; SINGLE EVENT UPSET (SEU); SINGLE EVENT UPSETS (SEUS);

DESIGN; DIGITAL STORAGE; FLASH MEMORY; LOGIC DEVICES; NETWORKS (CIRCUITS); SPACE RESEARCH;

OPTIMIZATION;

EID: 46149126905     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2006.320137     Document Type: Conference Paper

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