Adaptive techniques for overcoming performance degradation due to aging in CMOS circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 19, Issue 4, 2011, Pages 603-614

  Kumar, Sanjay V ^a   Kim, Chris H ^a   Sapatnekar, Sachin S ^a  

^a University of Minnesota   (United States)

Author keywords

Aging; Circuit synthesis; CMOS digital integrated circuits; Degradation; Digital circuits; High K gate dielectrics; MOSFETs; Negative bias temperature instability; Niobium compounds; Titanium compounds

Indexed keywords

AGING; CIRCUIT SYNTHESIS; CMOS DIGITAL INTEGRATED CIRCUITS; HIGH-K GATE DIELECTRICS; MOSFETS; NEGATIVE BIAS TEMPERATURE INSTABILITY;

CMOS INTEGRATED CIRCUITS; DEGRADATION; DIELECTRIC DEVICES; GATE DIELECTRICS; GATES (TRANSISTOR); HAFNIUM; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUITS; MOSFET DEVICES; NEGATIVE TEMPERATURE COEFFICIENT; NIOBIUM; NIOBIUM COMPOUNDS; THERMODYNAMIC STABILITY; TITANIUM; TITANIUM COMPOUNDS;

DIGITAL INTEGRATED CIRCUITS;

EID: 79953092815     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2009.2036628     Document Type: Article

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