Impact strain engineering on gate stack quality and reliability

Solid-State Electronics

Volumn 52, Issue 8, 2008, Pages 1115-1126

  Claeys, C ^a,b   Simoen, E ^a   Put, S ^a,b,c   Giusi, G ^d   Crupi, F ^d  

^a IMEC   (Belgium)

^b UNIVERSITY OF LEUVEN   (Belgium)

^c BELGIAN NUCLEAR RESEARCH CENTRE   (Belgium)

^d UNIVERSITY OF CALABRIA   (Italy)

Author keywords

Contact etch stop layer (CESL); Fully depleted SOI MOSFETs; Low field mobility; Low frequency noise; Silicon on Insulator (SOI); Strain engineering; Strained SOI (sSOI)

Indexed keywords

DIELECTRIC MATERIALS; LOGIC GATES; MOSFET DEVICES;

CARRIER (CO); CMOS TECHNOLOGIES; DRIVE CURRENTS; ELECTRICAL PARAMETERS; GATE OXIDE QUALITY; GATE STACKS; HIGH MOBILITY; LOCAL STRAINS; LOW FREQUENCY NOISE (1/F NOISE); NEGATIVE BIAS- TEMPERATURE-INSTABILITY (NBTI); RADIATION HARDNESS; STRAIN ENGINEERING; TIME-DEPENDENT DIELECTRIC BREAKDOWN (TDDB);

RELIABILITY;

EID: 48649104017     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2008.04.035     Document Type: Review

References (92)

1. Lee M.L., Fitzgerald E.A., Bulsara M.T., Currie M.T., and Lochtefeld A. Strained Si, SiGe, and Ge channels for high-mobility metal-oxide-semiconductor field-effect transistors. J Appl Phys 97 (2005) 011101/1-011101/27
2. 1-x layers with low threading dislocation densities grown on Si substrates. Appl Phys Lett 59 7 (1991) 811-813
3. Delhougne R., Meunier-Beillard P., Caymax M., Loo R., and Vandervorst W. Development of a new type of SiGe thin strain relaxed buffer based on the incorporation of a carbon-containing layer. Appl Surf Sci 224 1-4 (2004) 91-94
4. Agaiby R., Yang Y., Olsen S.H., O'Neill A.G., Eneman G., Verheyen P., et al. Quantifying self-heating effects with scaling in globally strained Si MOSFETs. Solid State Electron 51 (2007) 1473-1478
5. Isaacson D.M., Taraschi G., Pitera A.J., Ariel N., Langdo T.A., and Fitzgerald E.A. Strained-silicon and strained-silicon on silicon-germanium on silicon by relaxed buffer bonding. J Electrochem Soc 153 (2006) G134-G140
6. Claeys C, Simoen E. Germanium-based technologies: from materials to devices. Elsevier; 2007.
7. x source/drain technology for the 45-nm technology node and beyond. IEEE Trans Electron Dev 53 (2006) 1647-1655
8. Ang K-W, Chui K-J, Bliznetsov V, Wang Y, Wong L-Y, Tung C-H, et al. Thin body silicon-on-insulator n-MOSFET with silicon-carbon source/drain regions for performance enhancement. IEDM Technical Digest; 2005. p. 503-6.
9. Chui C.-J., Ang K.-W., Balasubramanian N., Li M.-F., Samudra G.S., and Yeo Y.-C. n-MOSFET with silicon-carbon source/drain for enhancement of carrier transport. IEEE Trans Electron Dev 54 (2007) 249-256
10. Chen C-H, Lee TL, Hou TH, Chen CL, Hsu JW, Cheng KL, et al. Stress memorization technique (SMT) by selectively strained-nitride capping for sub-65nm high-performance strained-Si device application. Symposium on VLSI Technology Digest of Technical Papers; 2004. p. 55-7.
11. Lu C.-Y., Lin H.-C., and Huang T.-Y. Impacts of uniaxial compressive strain on dynamic negative bias temperature instability of p-channel MOSFETs. Electrochem Solid-State Lett 9 (2006) G138-G140
12. Lai C.-M., Fang Y.-K., and Yeh W.-K. Stress technology impact on device performances and reliability for <1 0 0> sub-90 nm silicon-on-insulator complementary metal-oxide-semiconductor field-effect-transistors. Jpn J Appl Phys 45 (2006) 3053-3057
13. Liu C.-H., and Pan T.-M. Hot carrier and negative-bias temperature instability reliabilities of strained-Si MOSFETs. IEEE Trans Electron Dev 54 (2007) 1799-1803
14. Su P., and Kuo J.J.-Y. On the enhanced impact ionization in uniaxial strained p-MOSFETs. IEEE Electron Dev Lett 28 (2007) 649-651
15. Maeda S, Jin Y-S, Choi J-A, Oh S-Y, Lee H-W, Yoo J-Y, et al. Impact of mechanical stress engineering on flicker noise characteristics. Symposium on VLSI Technology Digest of Technical Papers; 2004. p. 102-3.
16. 2/TiN gate-stack p-MOSFETs. IEEE Electron Dev Lett 27 (2006) 508-510
17. Claeys C., Simoen E., Giusi G., and Crupi F. Does strain engineering impact the gate stack quality and reliability? Proceeding symposium on ULSI process integration 5. Electrochem Soc Trans 11-16 (2007) 101-114
18. Sun Y., Thompson S.E., and Nishida T. Physics of strain effects in semiconductors and metal-oxide-semiconductor field-effect transistors. J Appl Phys 101 (2007) 104503/1-104503/22
19. Goo J.-S., Xiang Q., Takamura Y., Arasnia F., Paton E.N., Besser P., et al. Band offset induced threshold variation in strained-Si nMOSFETs. IEEE Electron Dev Lett 24 (2003) 568-570
20. Lim J.-S., Thompson S.E., and Fossum J.G. Comparison of threshold-voltage shifts for uniaxial and biaxial tensile-stressed n-MOSFETs. IEEE Electron Dev Lett 25 (2004) 731-733
21. Thompson SE, Sun G, Wu K, Lim J, Nishida T. Key differences for process-induced uniaxial vs. substrate-induced biaxial stressed Si and Ge channel MOSFETs. IEDM Technical Digest; 2004. p. 221-4.
22. Zhao W., Seabaugh A., Adams V., Jovanovic D., and Winstead B. Opposing dependence of the electron and hole gate currents in SOI MOSFETs under uniaxial strain. IEEE Electron Dev Lett 26 (2005) 410-412
23. Hong C.-C., and Hwu J.-G. Degradation in metal-oxide-semiconductor structure with ultrathin gate oxide due to external compressive stress. Appl Phys Lett 79 (2001) 3797-3799
24. Yang X., Lim J., Sun G., Wu K., Nishida T., and Thompson S.E. Strain-induced changes in the gate tunneling currents in p-channel metal-oxide-semiconductor field-effect transistors. Appl Phys Lett 88 (2006) 052108/1-052108/3
25. Takagi S, Mizuno T, Tezuka T, Sugiyama N, Numata T, Usuda K, et al. Channel structure design, fabrication and carrier transport properties of strained-Si/SiGe-On-Insulator (strained-SOI) MOSFETs. IEDM Technical Digest; 2003. p. 57-60.
26. Onsongo D., Kelly D.Q., Dey S., Wise R.L., Cleavelin C.R., and Banerjee S.K. Improved hot-electron reliability in strained-Si nMOS. IEEE Trans Electron Dev 51 (2004) 2193-2199
27. Hoshii T., Sugahara S., and Takagi S. Effect of tensile strain on gate current of strained-Si n-channel metal-oxide-semiconductor field-effect transistors. Jpn J Appl Phys 46 (2007) 2122-2126
28. Yan L., Olsen S.H., Kanoun M., Agaiby R., and O'Neill A.G. Gate leakage mechanisms in strained Si devices. J Appl Phys 100 (2006) 104507/1-104507/6
29. Hsieh C.-Y., and Chen M.-J. Measurement of channel stress using gate direct tunneling current in uniaxially stressed nMOSFETs. IEEE Electron Dev Lett 28 (2007) 818-820
30. Waldron NS, Pitera AJ, Lee ML, Fitzgerald EA, del Alamo J. Impact ionization in strained-Si/SiGe heterostructures. IEDM Technical Digest; 2003. p. 813-6.
31. Lu MF, Chiang S, Liu A, Huang-Lu S, Yeh MS, Hwang JR et al. Hot carrier degradation in novel strained-Si nMOSFETs. In: Proceedings of the 42th annual international reliability of physics symposium; 2004. p. 18-22.
32. Waldron N.S., Pitera A.J., Lee M.L., Fitzgerald E.A., and del Alamo J. Positive temperature coefficient of impact ionization in strained-Si. IEEE Trans Electron Dev 52 (2005) 1627-1633
33. Irisawa T., Numata T., Sugiyama N., and Takagi S. On the origin of increase in substrate current and impact ionization efficiency in strained-Si n- and p-MOSFETs. IEEE Trans Electron Dev 52 (2005) 993-998
34. Chung SS, Huang DC, Tsai YJ, Lai CS, Tsai CH, Liu PW, et al. New observations on the uniaxial and biaxial strain-induced hot carrier and NBTI reliabilities for 65 nm node CMOS devices and beyond. IEDM Technical Digest; 2006. p. 325-8.
35. Watanabe N., Kojima T., Maeda Y., Nishisaka M., and Asano T. Breakdown voltage in uniaxially strained n-channel SOI MOSFET. Jpn J Appl Phys 43 (2004) 2134-2139
36. Nicholas G., Grasby T.J., Parker E.H.C., Whall T.E., and Skotnicki T. Impact ionization in strained Si devices. J Appl Phys 98 (2005) 104502/1-104502/4
37. Toh E.-H., Wang G.H., Lo G.-Q., Chan L., Samudra G., and Yeo Y.-C. Performance enhancement of n-channel impact-ionization metal-oxide-semiconductor transistor by strain engineering. Appl Phys Lett 90 (2007) 023505/1-023505/3
38. Toh E.-H., Wang G.H., Chan L., Lo G.-Q., Samudra G., and Yeo Y.-C. Strain and materials engineering for the I-MOS transistor with an elevated impact-ionization region. IEEE Trans Electron Dev 54 (2007) 2778-2785
39. Jenkins K.A., and Rim K. Measurement of the effect of self-heating in strained-silicon MOSFETs. IEEE Electron Dev Lett 23 (2002) 360-362
40. Olsen S.H., Escobedo-Cousin E., Varzgar J.B., Agaiby R., Seger J., Dobrosz P., Chattopadhyay S., Bull S.J., O'Neill A.G., Hellström P.-E., Edholm J., Östling M., Lyutovich K.L., Oehme M., and Kasper E. Control of self-heating in thin virtual substrate strained Si MOSFETs. IEEE Trans Electron Dev 53 (2006) 2296-2305
41. Maiti C.K., Samanta S.K., Chatterjee S., Dalapati G.K., and Bera L.K. Gate dielectrics on strained-Si/SiGe heterolayers. Solid-State Electron 48 (2004) 1369-1389
42. Lee S.-G., Kim Y.P., Lee H.-L., Jin B.J., Lee J.-W., Shin Y.G., et al. A comparative analysis of thermal gate oxide on strained Si/relaxed SiGe layer for reliability prediction of strained Si MOSFETs. Mat Sci Semicond Process 8 (2005) 215-218
43. Hua W.C., Lee M.H., Chen P.S., Maikap S., Liu C.W., and Chen K.M. Ge outdiffusion effect on the flicker noise in strained-Si nMOSFETs. IEEE Electron Dev Lett 25 (2004) 693-695
44. Hua W.-C., Lee M.H., Chen P.S., Tsai M.-J., and Liu C.W. Threading dislocation induced low frequency noise in strained-Si nMOSFETs. IEEE Electron Dev Lett 26 (2005) 667-669
45. Simoen E., Eneman G., Verheyen P., Loo R., De Meyer K., and Claeys C. Processing aspects in the low frequency noise of nMOSFETs on strained-silicon substrates. IEEE Trans Electron Dev 53 (2006) 1039-1047
46. von Haartman M., Malm B.G., Hellström P.-E., Östling M., Grasby T.J., Whall T.E., et al. Impact of strain and channel orientation on the low-frequency noise performance of Si n- and pMOSFETs. Solid-State Electron 51 (2007) 771-777
47. Malm BG, von Haartman M, Östling M. Influence of dislocations on low frequency noise in nMOSFETs fabricated on tensile strained virtual substrates. In: Tacano M, Yamamoto Y, Nakao M, editors. Proceedings of the 19th international conference on noise and fluctuations, American Inst Phys, CP922; 2007. p. 133-6.
48. Nishisaka M., Hamasaki Y., Shirata O., and Asano T. Cross-hatch related oxidation and its impact on performance of strained-Si MOSFETs. Jpn J Appl Phys 43 (2004) 1886-1890
49. Olsen S.H., O'Neill A.G., Norris D.J., Cullis A.G., Bull S.J., Chattopadhyay S., et al. Thermal oxidation of strained Si/SiGe: impact of surface morphology and effect on MOS devices. Mater Sci Eng B 109 (2004) 78-84
50. Kutsukake K., Usami N., Ujihara T., Fujiwara K., Sazaki G., and Nakajima K. On the origin of strain fluctuation in strained-Si grown on SiGe-on-insulator and SiGe virtual substrates. Appl Phys Lett 85 (2004) 1335-1337
51. Simoen E, Claeys C. Impact of strain engineering on the low-frequency noise performance of advanced MOSFETs. In: Proceedings of the eighth international conference on solid-state and integrated circuit technology, vol. 1; 2006. p. 120-3.
52. Contaret T., Boutchacha T., Ghibaudo G., Bœuf F., and Skotniki T. Drain and gate current low frequency noise in biaxially strained silicon n-MOSFETs with ultrathin gate oxides. Proc ULIS (2006) 119-122
53. Wang Y.P., Wu S.L., and Chang S.J. Low-frequency noise characteristics in strained-Si nMOSFETs. IEEE Electron Dev Lett 28 (2007) 36-38
54. Contaret T., Boutchacha T., Ghibaudo G., Bœuf F., and Skotniki T. Low frequency noise in biaxially strained silicon n-MOSFETs with ultrathin gate oxides. Solid-State Electron 51 (2007) 633-637
55. Dalapati G.K., Chattopadhyay S., Kwa K.S.K., Olsen S.H., Tsang Y.L., Agaiby R., et al. Impact of strained-Si thickness and Ge out-diffusion on gate oxide quality for strained-Si surface channel n-MOSFETs. IEEE Trans Electron Dev 53 (2006) 1142-1152
56. Simoen E., Eneman G., Verheyen P., Delhougne R., Loo R., De Meyer K., et al. On the beneficial impact of tensile-strained silicon substrates on the low-frequency noise of n-channel metal-oxide-semiconductor devices. Appl Phys Lett 86 (2005) 223509/1-223509/3
57. Yan L et al. Origins of noise in novel strained Si/SiGe n-MOSFETs. Unpublished.
58. Maji D., Duttagupta S.P., Rao R., Yeo C.C., and Cho B.J. Border-trap characterization in high-k strained-Si MOSFETs. IEEE Electron Dev Lett 28 (2007) 731-733
59. Kondo M., Sugii N., Miyamoto M., Hoshino Y., Hatori M., Hirasawa W., et al. Strained-silicon MOSFETs for analog applications: utilizing a supercritical-thickness strained layer for low leakage current and high breakdown voltage. IEEE Trans Electron Dev 53 (2006) 1226-1234
60. Ghibaudo G., and Boutchacha T. Electrical noise and RTS fluctuations in advanced CMOS devices. Microelectron Reliab 42 (2002) 572-582
61. b interface defects. Appl Phys Lett 82 (2003) 3038-3040
62. 2 entities probed by electron spin resonance. Appl Phys Lett 89 (2006) 152103/1-152103/3
63. Lu M.-P., Lee W.-C., and Chen M.-J. Channel-width dependence of low-frequency noise in process tensile-strained n-channel metal-oxide-semiconductor transistors. Appl Phys Lett 88 (2006) 063511/1-063511/3
64. Cheng C.Y., Fang Y.K., Hsieh J.C., Hsia H., Sheu Y.M., Lu W.T., et al. Investigation and localization of the SiGe source/drain (S/D) strain-induced defects in PMOSFET with 45-nm CMOS technology. IEEE Electron Dev Lett 28 (2007) 408-410
65. Wong K.M., Chim W.K., Ang K.W., and Yeo Y.C. Spatial distribution of interface trap density in strained channel transistors using the spread of the differential capacitance characteristics in scanning capacitance microscopy measurements. Appl Phys Lett 90 (2007) 153507/1-3
66. Giusi G., Crupi F., Simoen E., Eneman G., and Jurczak M. Performance and reliability of strained-silicon nMOSFETs with SiN cap layer. IEEE Trans Electron Dev 54 (2007) 78-82
67. Aigaby R, O'Neill AG, Olson SH, Simoen E, Claeys C. Unpublished.
68. Lukyanchikova N, Garbar N, Kudina V, Smolanka A, Simoen E, Claeys C. Behaviour of the 1/f noise and electron mobility in 65 nm FD SOI nMOSFETs employing different tensile-strain-inducing techniques. In: Tacano M, Yamamoto Y, Nakao M, editors. Noise and fluctuations, 19th international conference, American Institute of Physics; 2007. p. 39-42.
69. Duriez B, Tavel B, Boeuf F, Basso MT, Laplanche Y, Ortolland C, et al. Gate stack optimization for 65 nm CMOS low power and high performance platform. IEDM Technical Digest; 2004. p. 847-50.
70. Simoen E., Verheyen P., Shickova, Loo R., and Claeys C. On the low-frequency noise of pMOSFETs with embedded SiGe Source/Drain and Fully Silicided metal gate. IEEE Electron Dev Lett 28 (2007) 987-989
71. 0.3 pMOSFETs. IEEE Trans Electron Dev 50 (2003) 2513-2519
72. von Haartman M., Malm B.G., and Östling M. Comprehensive study on low-frequency noise and mobility in Si and SiGe pMOSFETs with high-κ gate dielectrics and TiN gate. IEEE Trans Electron Dev 51 (2006) 826-843
73. Yamamoto N., Iwata S., and Kume H. The influence of internal stresses in tungsten-gate electrodes on the degradation of MOSFET characteristics caused by hot carriers. IEEE Trans Electron Dev 34 (1987) 607-613
74. Miura H., Ikeda S., and Suzuki N. Effect of mechanical stress on reliability of gate-oxide film in MOS transistors. IEDM Tech Dig (1996) 743-746
75. Hamada A., Furusawa T., Saito N., and Takeda E. A new aspect of mechanical stress effects in scaled MOS devices. IEEE Trans Electron Devices 38 (1991) 895-900
76. Degraeve R, De Wolf I, Groeseneken G, Maes HE. Analysis of externally imposed stress effects on the hot-carrier-induced degradation of MOSFETs. In: Proceedings of annual international reliability of physics symposium IEEE/IRPS; 1994. p. 29-33.
77. Loh WY, Wang Q, Kong KW, Bera LK, Chan DSH, Lo GQ, et al. Device performance and reliability in strained nMOS with substrate bonding. Proceedings of ULIS; 2006. p. 165-8.
78. Lai C.-M., Fang Y.-K., Lin C.-T., and Yeh W.-K. The geometry effect of contact etch stop layer impact on device performance and reliability for 90-nm SOI nMOSFETs. IEEE Trans Electron Dev 53 (2006) 2779-2785
79. Lu C.-S., Lin H.-C., Huang J.-M., and Lee Y.-J. Impacts of a polycrystalline-silicon buffer layer on the performance and reliability of strained n-channel metal-oxide-semiconductor field-effect transistors with SiN capping. Appl Phys Lett 90 (2007) 122110/1-3
80. Ang K-W, Wan C, Chui K-J, Tung C-H, Balasubramanian N, Li M-F et al. Hot carrier reliability of strained N-MOSFET with lattice mismatched source-drain stressors. In: Proceedings of the annual international reliability of physics symposium; 2007. p. 684-5.
81. y) source/drain stressors and its orientation dependence. IEEE Electron Dev Lett 28 (2007) 996-999
82. Samanta S.K., Chatterjee S., Choi W.K., Bera L.K., Banerjee H.D., and Maiti C.K. Reliability of ultrathin (<2 nm) oxides on strained SiGe heterolayers. Semicond Sci Technol 18 (2003) 33-38
83. Griffoni A., Gerardin S., Cester A., Paccagnella A., Simoen E., and Claeys C. Effects of heavy-ion strikes on fully depleted SOI MOSFETs with ultra-thin gate oxide and different strain-inducing techniques. IEEE Trans Nucl Sci 54 (2007) 2257-2263
84. 0.2 pMOSFETs under Fowler-Nordheim stress. IEEE Trans Electron Dev 50 (2003) 1152-1156
85. Jiang Y., Loh W.Y., Chan D.S.H., Xiong Y.Z., Ren C., Lim Y.F., et al. Flicker noise and its degradation characteristics under electrical stress in MOSFETs with thin strained-Si/SiGe dual-quantum well. IEEE Electron Dev Lett 28 (2007) 603-605
86. Lu C.-Y., Lin H.-C., Chang Y.-F., and Huang T.-Y. Device characteristics and aggravated negative bias temperature instability in p-channel metal-oxide-semiconductor field-effect transistors with uniaxial compressive strain. Jpn J Appl Phys 45 (2006) 3064-3069
87. Pan T.-M. Carrier mobility characteristics and negative bias temperature instability reliability in strained-Si p-type metal-oxide-semiconductor field-effect transistors. Electrochem Solid-State Lett 9 (2006) G351-G353
88. Shickova A., Kaczer B., Verheyen P., Eneman G., San Andres E., Jurczak M., et al. Negligible effect of process-induced strain on intrinsic NBTI behavior. IEEE Electron Dev Lett 28 (2007) 242-244
89. Shickova A., Kaczer B., Simoen E., Verheyen P., Eneman G., Jurczak M., et al. Dielectric quality and reliability of FUSI/HfSiON devices with process induced strain. Microelectron Eng 9-10 (2007) 1906-1909
90. Put S, Simoen E, Augendre E, Claeys C, Van Uffelen M, Leroux P. Comparison of the radiation behavior of 65 nm fully depleted Silicon-on-Insulator MOSFETs employing different tensile-strain-inducing techniques. Proc RADECS Workshop (in press).
91. Put S., Simoen E., Collaert N., Claeys C., Van Uffelen M., and Leroux P. Geometry and strain dependence of the proton radiation behavior of MuGFET devices. IEEE Trans Nucl Sci 54 (2007) 2227-2232
92. 60Co gamma-ray irradiation on strained silicon on insulator. J Appl Phys 102 (2007) 074507/1-5