-
1
-
-
0033683205
-
Multiple SiGe well: A new channel architecture for improving both NMOS and PMOS performances
-
J. Alieu, T. Skotnicki, E. Josse, J.-L. Regolini, and G. Bremond, "Multiple SiGe well: A new channel architecture for improving both NMOS and PMOS performances," in VLSI Symp. Tech. Dig., 2000, pp. 130-131.
-
(2000)
VLSI Symp. Tech. Dig
, pp. 130-131
-
-
Alieu, J.1
Skotnicki, T.2
Josse, E.3
Regolini, J.-L.4
Bremond, G.5
-
2
-
-
84907907490
-
Multiple SiGe quantum wells - Novel channel architecture for 0.12 um CMOS
-
J. Alieu, T. Skotnicki, J.-L. Regolini, and G. Bremond, "Multiple SiGe quantum wells - Novel channel architecture for 0.12 um CMOS," in Proc. ESSDERC, 1999, pp. 292-295.
-
(1999)
Proc. ESSDERC
, pp. 292-295
-
-
Alieu, J.1
Skotnicki, T.2
Regolini, J.-L.3
Bremond, G.4
-
3
-
-
0347968283
-
0.3 pMOSFETs
-
Dec
-
0.3 pMOSFETs," IEEE Trans. Electron Devices, vol. 50, no. 2, pp. 2513-2519, Dec. 2003.
-
(2003)
IEEE Trans. Electron Devices
, vol.50
, Issue.2
, pp. 2513-2519
-
-
von Haartman, M.1
Lindgren, A.C.2
Hellstrom, P.E.3
Malm, B.G.4
Zhang, S.L.5
Ostling, M.6
-
4
-
-
0032687249
-
DC and low-frequency noise characteristics of SiGe p-channel FET's designed for 0.13 μm technology
-
Jul
-
S. Okhonin, M. A. Py, B. Georgescu, H. Fischer, and L. Risch, "DC and low-frequency noise characteristics of SiGe p-channel FET's designed for 0.13 μm technology," IEEE Trans. Electron Devices, vol. 46, no. 7, pp. 1514-1517, Jul. 1999.
-
(1999)
IEEE Trans. Electron Devices
, vol.46
, Issue.7
, pp. 1514-1517
-
-
Okhonin, S.1
Py, M.A.2
Georgescu, B.3
Fischer, H.4
Risch, L.5
-
5
-
-
0035456675
-
x p-channel metal-oxide-semiconductor field-effect transistors
-
Sep
-
x p-channel metal-oxide-semiconductor field-effect transistors," Jpn. J. Appl. Phys., vol. 40, no. 9A, pp. 5290-5293, Sep. 2001.
-
(2001)
Jpn. J. Appl. Phys
, vol.40
, Issue.9 A
, pp. 5290-5293
-
-
Tsuchiya, T.1
Matsuura, T.2
Murota, J.3
-
6
-
-
0032662603
-
x MOSFET's
-
Jul
-
x MOSFET's," IEEE Trans. Electron Devices, vol. 46, no. 7, pp. 1484-1486, Jul. 1999.
-
(1999)
IEEE Trans. Electron Devices
, vol.46
, Issue.7
, pp. 1484-1486
-
-
Lambert, A.D.1
Alderman, B.2
Lander, R.J.P.3
Parker, E.H.C.4
Whall, T.E.5
-
7
-
-
84907512923
-
0.36/Si pMOSFETs with enhanced voltage gain and low 1/ f noise
-
Nurenburg, Germany, Sep. 11-13
-
0.36/Si pMOSFETs with enhanced voltage gain and low 1/ f noise," in Proc. ESSDERC, Nurenburg, Germany, Sep. 11-13, 2001, pp. 179-182.
-
(2001)
Proc. ESSDERC
, pp. 179-182
-
-
Prest, M.J.1
Palmer, M.J.2
Braithwaite, G.3
Grasby, T.J.4
Phillips, P.J.5
Mironov, O.A.6
Parker, E.H.C.7
Whall, T.E.8
-
8
-
-
0037480716
-
0.2 pMOSFETs under Fowler-Nordheim stress
-
Apr
-
0.2 pMOSFETs under Fowler-Nordheim stress," IEEE Trans. Electron Devices, vol. 50, no. 4, pp. 1152-1156, Apr. 2003.
-
(2003)
IEEE Trans. Electron Devices
, vol.50
, Issue.4
, pp. 1152-1156
-
-
Song, Y.J.1
Lim, J.W.2
Mheen, B.3
Kim, S.H.4
Bae, H.C.5
Kang, J.Y.6
Kim, J.H.7
Song, J.I.8
Park, K.W.9
Shim, K.H.10
-
9
-
-
0142077567
-
High-performance strained Si/SiGe pMOS devices with multiple quantum wells
-
Dec
-
N. Collaert, P. Verheyen, K. De Meyer, R. Loo, and M. Caymax, "High-performance strained Si/SiGe pMOS devices with multiple quantum wells," IEEE Trans. Nanotechnol., vol. 1, no. 4, pp. 190-194, Dec. 2002.
-
(2002)
IEEE Trans. Nanotechnol
, vol.1
, Issue.4
, pp. 190-194
-
-
Collaert, N.1
Verheyen, P.2
De Meyer, K.3
Loo, R.4
Caymax, M.5
-
10
-
-
17044429048
-
Lattice strain analysis of transistor structures with silicon-germanium and silicon-carbon source/drain stressors
-
Feb
-
K. W. Ang, K. J. Chui, V. Bliznetsov, C. H. Tung, A. Du, N. Balasubramanian, G. Samudra, M. F. Li, and Y. C. Yeo, "Lattice strain analysis of transistor structures with silicon-germanium and silicon-carbon source/drain stressors," Appl. Phys. Lett., vol. 86, no. 9, p. 0931021, Feb. 2005.
-
(2005)
Appl. Phys. Lett
, vol.86
, Issue.9
, pp. 0931021
-
-
Ang, K.W.1
Chui, K.J.2
Bliznetsov, V.3
Tung, C.H.4
Du, A.5
Balasubramanian, N.6
Samudra, G.7
Li, M.F.8
Yeo, Y.C.9
-
11
-
-
0034317664
-
Critical discussion on the unified 1/f noise model for MOSFETs
-
Nov
-
E. P. Vandamme and L. K. J. Vandamme, "Critical discussion on the unified 1/f noise model for MOSFETs," IEEE Trans. Electron Devices, vol. 47, no. 11, pp. 2146-2152, Nov. 2000.
-
(2000)
IEEE Trans. Electron Devices
, vol.47
, Issue.11
, pp. 2146-2152
-
-
Vandamme, E.P.1
Vandamme, L.K.J.2
|