Control of self-heating in thin virtual substrate strained Si MOSFETs

IEEE Transactions on Electron Devices

Volumn 53, Issue 9, 2006, Pages 2296-2303

  Olsen, Sarah H ^b   Escobedo Cousin, Enrique ^b   Varzgar, John B ^b   Agaiby, Rimoon ^a,b   Seger, Johan ^b   Dobrosz, Peter ^b   Chattopadhyay, Sanatan ^b   Bull, Steve J ^b   O'Neill, Anthony G ^b   Hellström, Per Erik ^c   Edholm, Jonas ^c   Östling, Mikael ^c   Lyutovich, Klara L ^d   Oehme, Michael ^d   Kasper, Erich ^d  

^a IEEE

^b NEWCASTLE UNIVERSITY   (United Kingdom)

^c ROYAL INSTITUTE OF TECHNOLOGY   (Sweden)

^d UNIVERSITY OF STUTTGART   (Germany)

Author keywords

MOSFETs; Self heating; Silicon germanium; Strained silicon; Virtual substrate

Indexed keywords

ELECTRIC RESISTANCE; GATES (TRANSISTOR); SILICON COMPOUNDS; SUBSTRATES; THERMAL EFFECTS;

SELF-HEATING; SILICON GERMANIUM; STRAINED SILICON; VIRTUAL SUBSTRATES;

MOSFET DEVICES;

EID: 33947097365     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2006.881049     Document Type: Article

References (50)

1. M. V. Fischetti and S. E. Laux, "Band structure, deformation potentials, and carrier mobility in strained Si, Ge, and SiGe alloys," J. Appl. Phys., vol. 80; no. 4, pp. 2234-2252, Aug. 1996.
2. S. Thompson et al., "A 90-nm logic technology featuring strained-silicon," IEEE Trans. Electron Devices, vol. 51, no. 11, pp. 1790-1797, Nov. 2004.
3. A. Shimizu et al., "Local mechanical-stress control (LMC): A new technique for CMOS-performance enhancement," in IEDM Tech. Dig., 2001, pp. 433-136.
4. K. Ota et al., "Novel locally strained channel technique for high performance 55 nm CMOS," in IEDM Tech. Dig., 2002, pp. 27-30.
5. V. Chan et al., "High speed 45 nm gate length CMOSFETs integrated into a 90 nm bulk technology incorporating strain engineering," in IEDM Tech. Dig., 2003, pp. 77-80.
6. C.-H. Ge et al., "Process-strained Si (PSS) CMOS technology featuring 3-D strain engineering," in IEDM Tech. Dig., 2003, pp. 57-60.
7. S. Dhar, H. Kosina, V. Palankovski, S. E. Ungersboeck, and S. Selberherr, "Electron mobility model for strained Si devices," IEEE Trans. Electron Devices, vol. 52, no. 4, pp. 527-533, Apr. 2005.
8. 2/TiN gate stack," IEEE Trans. Electron Devices, vol. 53, no. 3, pp. 449-456, Mar. 2006.
9. M. Kondo et al., "High performance RF power LDMOSFETs for cellular handsets formed in thick-strained-Si/relaxed-SiGe structure," in IEDM Tech. Dig., 2005, pp. 365-368.
10. O. Weber et al., "Strained Si and Ge MOSFETs with high-k/metal gate stack for high mobility dual channel CMOS," in IEDM Tech. Dig., 2005, pp. 137-140.
11. K. Rim et al., "Characteristics and device design of sub-100 nm strained Si n- and p-MOSFETs," in VLSI Symp. Tech. Dig., 2002, pp. 98-99.
12. N. Sugii, D. Hisamoto, N. Yokoyama, and S. Kimura, "Performance enhancement of strained-Si MOSFETs fabricated on a chemical-mechanical-polished SiGe substrate," IEEE Trans. Electron Devices, vol. 49, no. 12, pp. 2237-2243, Dec. 2002.
13. S. H. Olsen et al., "High performance strained Si/SiGe n-channel MOSFETs fabricated using a novel CMOS architecture," IEEE Trans. Electron Devices, vol. 50, no. 9, pp. 1961-1969, Sep. 2003.
14. 0.5 for symmetric mobility p-type and n-type metal-oxide-semiconductor field-effect transistors," Appl. Phys. Lett., vol. 80, no. 20, pp. 4202-4204, Jun. 2003.
15. D. J. Paul, "Silicon-germanium strained layer materials in microelectronics," Adv. Mater., vol. 11, no. 3, pp. 191-204, Mar. 1999.
16. J. P. Dismukes, L. Ekstrom, E. F. Steigmeiter, I. Kudman, and D. S. Beers, "Thermal and elastic properties of heavily doped Ge-Si alloys up to 1300 K," J. Appl. Phys., vol. 35, no. 10, pp. 2899-2907, 1964.
17. K. Michelakis et al., "SiGe differential pair," in Proc. ISCAS, 2001, pp. 679-682.
18. 1-x layers with low threading dislocation densities grown on Si substrates," Appl. Phys. Lett., vol. 59, no. 7, pp. 811-813, Aug. 1991.
19. J. M. Hartmann, B. Gallas, J. Zhang, and J. J. Harris, "Gas-source molecular beam epitaxy of SiGe virtual substrates - II: Strain relaxation and surface morphology," Semicond. Sci. Technol., vol. 15, no. 4, pp. 370-377, Apr. 2000.
20. T. Hackbarth et al., "Reduced self-heating in Si/SiGe field-effect transistors on thin virtual substrates prepared by low-energy plasma-enhanced chemical vapor deposition," Appl. Phys. Lett., vol. 83, no. 26, pp. 5464-5466, 2003.
21. E. Kasper, K. Lyutovich, M. Bauer, and M. Oehme, "New virtual substrate concept for vertical MOS transistors," Thin Solid Films, vol. 336, no. 1/2, pp. 319-322, Dec. 1998.
22. M. Bauer et al., "Relaxed SiGe buffers with thicknesses below 0.1μm," Thin Solid Films, vol. 369, no. 1/2, pp. 152-156, Jul. 2000.
23. K. Lyutovich et al., "Thin SiGe buffers with high Ge content for n-MOSFETs," Mater. Sci. Eng. B, vol. 89, no. 1-3, pp. 341-345, Feb. 2002.
24. E. Kasper and K. Lyutovich, "Strain adjustment with thin virtual substrates," Solid State Electron., vol. 48, no. 8, pp. 1257-1263, Aug. 2004.
25. T. Hackbarth et al., "High frequency n-type MOSFETs on ultra-thin virtual SiGe substrates," Solid State Electron., vol. 47, no. 7, pp. 1179-1182, Jul. 2003.
26. K. Sawano et al., "Fabrication of high-quality strain-relaxed thin SiGe layers on ion-implanted Si substrates," Appl. Phys. Lett., vol. 85, no. 13, pp. 2514-2516, Sep. 2004.
27. R. Delhougne, P. Meunier-Beillard, M. Caymax, R. Loo, and W. Vanderworst, "Development of a new type of SiGe thin strain relaxed buffer based on the incorporation of a carbon-containing layer," Appl. Surf. Sci., vol. 224, no. 1-4, pp. 91-94, Mar. 2004.
28. x virtual substrate," Microelectron. J., vol. 35, no. 12, pp. 969-971, Dec. 2004.
29. G. Eneman et al., "Fabrication of strained Si NMOS transistors on thin buffer layers with selective and non-selective epitaxial growth techniques," Mater. Sci. Semicond. Process., vol. 8, no. 1-3, pp. 337-342, Feb.-Jun. 2005.
30. A. Oishi et al., "High performance CMOSFET technology for 45 nm generation and scalability of stress-induced mobility enhancement techniques," in IEDM Tech. Dig., 2005, pp. 232-239.
31. 1-x films," Appl. Phys. Lett., vol. 61, no. 11, pp. 1293-1295, Sep. 1992.
32. x alloy layers," Appl. Phys. Lett., vol. 64, no. 24, pp. 3305-3307, Jun. 1994.
33. PeakFit Software, Aspire Software International. [Online]. Available: www.aspiresoftwareintl.com
34. P. Dobrosz, S. J. Bull, S. H. Olsen, and A. G. O'Neill, "The use of Roman spectroscopy to identify strain and strain relaxation in strained Si/SiGe structures," Surf. Coatings Technol., vol. 200, no. 5/6, pp. 1755-1760, Nov. 2005.
35. 0.4 strain relaxed buffers," Mater. Sci. Semicond. Process., vol. 8, no. 1-3, pp. 149-153, Feb.-Jun. 2005.
36. D. G. Schimmel, "Defect etch for (100) silicon evaluation," J. Electrochem. Soc., vol. 126, no. 3, pp. 479-483, Mar. 1979.
37. S. H. Olsen et al., "Study of strain relaxation in Si/SiGe metal-oxide-semiconductor field-effect transistors," J. Appl. Phys., vol. 97, no. 11, pp. 114504-1-114504-9,2005.
38. International Technology Roadmap for Semiconductors. (2005). [Online]. Available: www.itrs.net
39. 0.25
40. u film," J. Appl. Phys., vol. 96, no. 12, pp. 7179-7182, Dec. 2004.
41. S. H. Olsen et al., "Optimization of alloy composition for high performance strained Si/SiGe n-channel MOSFETs," IEEE Trans. Electron Devices, vol. 51, no. 7, pp. 1156-1162, Jul. 2004.
42. B. M. Tenbroek, M. S. L. Lee, W. Redman-White, J. T. Bunyan, and M. J. Uren, "Self-heating effects in SOI MOSFET's and their measurement by small signal conductance techniques," IEEE Trans. Electron Devices, vol. 43, no. 12, pp. 2240-2248, Dec. 1996.
43. K. A. Jenkins and K. Rim, "Measurement of the effect of self-heating in strained-silicon MOSFETs," IEEE Electron Device Lett., vol. 23, no. 6, pp. 360-362, Jun. 2002.
44. K. Rim, J. L. Höyt, and J. F. Gibbons, "Fabrication and analysis of deep submicron strained-Si n-MOSFET's," IEEE Trans. Electron Devices, vol. 47, no. 7, pp. 1406-1415, Jul. 2000.
45. N. R. Zangenberg, J. Fage-Pederson, J. L. Hansen, and A. N. Larsen, "Boron and phosphorus diffusion in strained and relaxed Si and SiGe," J. Appl. Phys., vol. 94, no. 6, pp. 3883-3890, Sep. 2003.
46. J. G. Fiorenza et al., "Film thickness constraints for manufacturable strained Si CMOS," Semicond. Sci. Technol., vol. 19, no. 1, pp. L4-L8, Jan. 2004.
47. T. Perova et al., "Micro-Raman investigations of the degree of relaxation in thin SiGe buffer layers with high Ge content," J. Mater. Sci., Mater. Electron., vol. 14, no. 5-7, pp. 441-444, May 2003.
48. E. H. Nicollian and J. R. Brews, MOS (Metal Oxide Semiconductor) Physics and Technology. New York: Wiley, 1982.
49. S. Takagi, A. Toriumi, M. Iwase, and H. Tango, "On the universality of inversion layer mobility in Si MOSFET's - Part I: Effects of substrate impurity concentration," IEEE Trans. Electron Devices, vol. 41, no. 12, pp. 2357-2362, Dec. 1994.
50. S. H. Olsen et al., "Impact of virtual substrate quality on performance enhancements in strained Si/SiGe heterojunction n-channel MOSFETs," Solid State Electron., vol. 47, no. 8, pp. 1289-1295, Aug. 2003.