Comprehensive study on low-frequency noise and mobility in Si and SiGe pMOSFETs with high-κ gate dielectrics and TiN gate

IEEE Transactions on Electron Devices

Volumn 53, Issue 4, 2006, Pages 836-843

  von Haartman, Martin ^a   Malm, B Gunnar ^a   Østling, Mikael ^a  

^a ROYAL INSTITUTE OF TECHNOLOGY   (Sweden)

Author keywords

1 f noise; High dielectrics; Low frequency noise; Metal gate; MOSFETs; SiGe

Indexed keywords

DIELECTRIC MATERIALS; GATES (TRANSISTOR); POLYSILICON; SEMICONDUCTING SILICON; SEMICONDUCTING SILICON COMPOUNDS; SEMICONDUCTOR DEVICE MODELS; TITANIUM NITRIDE;

GATE DIELECTRICS; LOW-FREQUENCY NOISE; METAL GATE;

MOSFET DEVICES;

EID: 33645768992     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2006.870276     Document Type: Article

References (45)

1. International Technology Roadmap for Semiconductors (ITRS), 2003. [Online]. Available: http://public.itrs.net/
2. G. D. Wilk, R. M. Wallace, and J. M. Anthony, "High-κ gate dielectrics: Current status and materials properties considerations," J. Appl. Phys., vol. 89, no. 10, pp. 5243-5275, May 2001.
3. E. P. Gusev, D. A. Buchanan, E. Cartier, A. Kumar, D. DiMaria, S. Guha, A. Callegari, S. Zafar, P. C. Jamison, D. A. Neumayer, M. Copel, M. A. Gribelyuk, H. Okron-Schmidt, C. D'Emic, P. Kozlowski, K. Chan, N. Bojarczuk, L. Å. Ragnarsson, P. Ronsheim, K. Rim, R. J. Fleming, A. Mocuta, and A. Ajmera, "Ultrathin high-κ gate stacks for advanced CMOS devices," in IEDM Tech. Dig., 2001, pp. 451-454.
4. B. Guillaumot, X. Garros, F. Lime, K. Oshima, B. Tavel, J. A. Chroboczek, P. Masson, R. Truche, A. M. Papon, F. Martin, J. F. Damlencourt, S. Maitrejean, M. Rivoire, C. Leroux, S. Christoloveanu, G. Ghibaudo, J. L. Autran, T. Skotnicki, and S. Deleonibus, "75 nm damascene metal gate and high-κ integration for advanced CMOS devices," in IEDM Tech. Dig., 2002, pp. 355-358.
5. 2 on the device performance of high-κ based transistors," in IEDM Tech. Dig., 2003, pp. 87-90.
6. 2-gated NMOSFETs," IEEE Electron Device Lett., vol. 25, no. 2, pp. 89-91, Feb. 2004.
7. 5 as gate dielectrics," Microelectron. Reliab., vol. 41, no. 9, pp. 1361-1366, Sep. 2001.
8. 0.3 surface channel pMOSFETs with a metal/high-κ gate stack," in Proc. ICNF, Prague, Czech Republic, 2003, pp. 381-384.
9. T. Ishikawa, S. Tsujikawa, S. Saito, D. Hisamoto, and S. Kimura, "Direct evaluation of an interfacial layer in high-κ gate dielectrics by 1/f noise measurements," in Proc. SSDM, 2003, pp. 14-15.
10. 2 gate dielectric," in Proc. Electrochem. Society Meeting, 2003, vol. 22, pp. 319-331.
11. 3 gate dielectrics," in Proc. Electrochem. Society Meeting, 2003, vol. 22, pp. 415-423.
12. y/Si(100) gate stacks," Appl. Phys. Lett., vol. 83, no. 25, pp. 5232-5234, Dec. 2003.
13. 2 dual-layer gate dielectric nMOSFETs with different interfacial oxide thickness," IEEE Trans. Electron Devices, vol. 51, no. 5, pp. 780-784, May 2004.
14. 2 n-MOSFETs," in Proc. Electrochem. Society Meeting, 2004, vol. 1, pp. 292-303.
15. x gate stacks," IEEE Trans. Electron Devices, vol. 51, no. 10, pp. 1679-1687, Oct. 2004.
16. 2 dual layer gate dielectrics," IEEE Electron Device Lett., vol. 24, no. 2, pp. 87-89, Feb. 2003.
17. S. Saito, D. Hisamoto, S. Kimura, and M. Hiratani, "Unified mobility model for high-κ gate stacks," in IEDM Tech. Dig., 2003, pp. 797-800.
18. M. V. Fischetti, D. A. Neumayer, and E. A. Cartier, "Effective electron mobility in Si inversion layers in metal-oxide-semiconductor systems with a high-κ insulator: The role of remote phonon scattering," J. Appl. Phys., vol. 90, no. 9, pp. 4587-4608, Nov. 2001.
19. Z. Ren, M. V. Fischetti, E. P. Gusev, E. A. Cartier, and M. Chudzik, "Inversion channel mobility in high-κ high performance MOSFETs," in IEDM Tech. Dig., 2003, pp. 793-796.
20. T. Yamaguchi, R. Iijima, T. Ino, A. Nishiyama, H. Satake, and N. Fukushima, "Additional scattering effects for mobility degradation in Hf-silicate gate MISFETs," in IEDM Tech. Dig., 2002, pp. 621-624.
21. L. K. J. Vandamme, X. Li, and D. Rigaud, "1/f noise in MOS devices, mobility or number fluctuations?" IEEE Trans. Electron Devices, vol. 41, no. 11, pp. 1936-1945, Nov. 1994.
22. G. Ghibaudo and T. Boutchacha, "Electrical noise and RTS fluctuations in advanced CMOS devices," Microelectron. Reliab., vol. 42, no. 4, pp. 573-582, Apr. 2002.
23. 2 gate stack n-MOSFETs," Solid State Electron., vol. 49, no. 5, pp. 702-707, May 2005.
24. M. Valenza, A. Hoffmann, D. Sodini, A. Laigle, F. Martinez, and D. Rigaud, "Overview of the impact of downscaling technology on 1/f noise in p-MOSFETs to 90 nm," Proc. Inst. Elect. Eng. - Circuits Devices Syst., vol. 151, no. 2, pp. 102-110, Apr. 2004.
25. G.-W. Lee, J.-H. Lee, H.-W. Lee, M.-K. Park, D.-G. Kang, and H.-K. Youn, "Trap evolutions of metal/oxide/silicon field-effect transistors with high-κ gate dielectric using charge pumping method," Appl. Phys. Lett., vol. 81, no. 11, pp. 2050-2052, Sep. 2002.
26. C. Leroux, J. Mitard, G. Ghibaudo, X. Garros, G. Reimbold, B. Guillaumot, and F. Martin, "Characterization and modelling of hysteresis phenomena in high κ dielectrics," in IEDM Tech. Dig., 2004, pp. 737-740.
27. 3 dielectrics on the trap-depth profiles in MOS devices investigated by the charge-pumping method," IEEE Trans. Electron Devices, vol. 51, no. 12, pp. 2252-2255, Dec. 2004.
28. 0.3 surface-channel pMOSFETs," IEEE Electron Device Lett., vol. 24, no. 3, pp. 171-173, Mar. 2003.
29. 3 gate dielectrics," Solid State Electron., vol. 48, no. 12, pp. 2271-2275, Dec. 2004.
30. M. von Haartman, B. G. Malm, P.-E. Hellström, and M. Östling, "Noise in Si and SiGe pMOSFETs with high-κ gate dielectrics," in Proc. ICNF, 2005, pp. 225-230.
31. S. I. Takagi, A. Toriumi, M. Iwase, and H. Tango, "On the universality of inversion layer mobility in Si MOSFET's: Part I - Effects of substrate impurity concentration," IEEE Trans. Electron Devices, vol. 41, no. 12, pp. 2357-2362, Dec. 1994.
32. D. K. Schroder, Semiconductor Material and Device Characterization, 2nd ed. New York: Wiley, 1998, p. 546.
33. R. Chau, S. Datta, M. Doczy, B. Doyle, J. Kavalieros, and M. Metz, "High-κ/metal-gate stack and its MOSFETs characteristics," IEEE Electron Device Lett., vol. 25, no. 6, pp. 408-410, Jun. 2004.
34. 2/TiN surface channel n- and p-MOSFETs," in IEDM Tech. Dig., 2004, pp. 867-870.
35. x alloys," IEEE Trans. Electron Devices, vol. 40, no. 11, pp. 1990-1996, Nov. 1993.
36. G. Mazzoni, A. L. Lacaita, L. M. Perron, and A. Pirovano, "On surface roughness-limited mobility in highly doped n-MOSFET's," IEEE Trans. Electron Devices, vol. 46, no. 7, pp. 1423-1428, Jul. 1999.
37. 2 stack," in IEDM Tech. Dig., 2004, pp. 821-824.
38. K. K. Hung, P. K. Ko, C. Hu, and Y. C. Cheng, "A unified model for the flicker noise in metal-oxide-semiconductor field-effect transistors," IEEE Trans. Electron Devices, vol. 37, no. 3, pp. 654-665, Mar. 1990.
39. E. P. Vandamme and L. K. J. Vandamme, "Critical discussion on unified 1/f noise models for MOSFETs," IEEE Trans. Electron Devices, vol. 47, no. 11, pp. 2146-2152, Nov. 2000.
40. S. T. Martin, G. P. Li, E. Worley, and J. White, "The gate bias and geometry dependence of random telegraph signal amplitudes," IEEE Electron Device Lett., vol. 18, no. 9, pp. 444-446, Sep. 1997.
41. 2 gate dielectric n-channel metal-oxide-semiconductor field-effect transistors," Appl. Phys. Lett., vol. 85, no. 6, pp. 1057-1059, Aug. 2004.
42. F. N. Hooge, "1/f noise sources," IEEE Trans. Electron Devices, vol. 41, no. 11, pp. 1926-1935, Nov. 1994.
43. M. J. Deen and O. Marinov, "Effect of forward and reverse substrate biasing on low-frequency noise in silicon PMOSFETs," IEEE Trans. Electron Devices, vol. 49, no. 3, pp. 409-413, Mar. 2002.
44. 0.3 pMOSFETs," IEEE Trans. Electron Devices, vol. 50, no. 12, pp. 2513-2519, Dec. 2003.
45. 3 gate dielectrics," Solid State Electron., vol. 49, no. 6, pp. 907-914, Jun. 2005.