Stress memorization technique (SMT) by selectively strained-nitride capping for sub-65nm high-performance strained-Si device application

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 2004, Pages 56-57

  Chen, Chien Hao ^a   Lee, T L ^a   Hou, T H ^a   Chen, C L ^a   Chen, C C ^a   Hsu, J W ^a   Cheng, K L ^a   Chiu, Y H ^a   Tao, H J ^a   Jin, Y ^a   Diaz, C H ^a   Chen, S C ^a   Liang, M S ^a  

^a TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY   (Taiwan)

Author keywords

Nitride; SMT; Stained Si; Stress

Indexed keywords

NMOS; PERFORMANCE DEGRADATION; STRAINED-SI; STRESS MEMORIZATION TECHNIQUE (SMT);

ANNEALING; CHEMICAL VAPOR DEPOSITION; CMOS INTEGRATED CIRCUITS; HOLE MOBILITY; MOSFET DEVICES; NITRIDES; OPTIMIZATION; RECRYSTALLIZATION (METALLURGY); STRESS ANALYSIS; TRANSCONDUCTANCE;

SEMICONDUCTING SILICON;

EID: 4544382132     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. J.L. Hoyt, et al., IEDM Tech. Dig., p. 23, 2002.
2. T.Mizuno et al., VLSI Symp. p. 106, 2002.
3. K. Ota, et al., IEDM Tech. Dig, p.27, 2002.
4. Shinya.Ito, et al., IEDM Tech. Dig, p. 247, 2000.
5. A. Shimizu., et al., IEDM Tech. Dig., p. 433, 2003.