Border-trap characterization in high-κ strained-Si MOSFETs

IEEE Electron Device Letters

Volumn 28, Issue 8, 2007, Pages 731-733

  Maji, Debabrata ^a   Duttagupta, S P ^a   Rao, V Ramgopal ^a   Yeo, Chia Ching ^b   Cho, Byung Jin ^b  

^a INDIAN INSTITUTE OF TECHNOLOGY BOMBAY   (India)

^b NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

Author keywords

1 f noise; Border traps; Charge pumping; Hysteresis; Interface trapping; Strained Si

Indexed keywords

DRAIN CURRENT; GATE DIELECTRICS; HYSTERESIS; SEMICONDUCTING SILICON;

BORDER TRAP; CHARGE PUMPING; INTERFACE TRAPPING;

MOSFET DEVICES;

EID: 34547751876     PISSN: 07413106     EISSN: None     Source Type: Journal    
DOI: 10.1109/LED.2007.902086     Document Type: Article

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