-
1
-
-
0000793139
-
Cramming more components onto integrated circuits
-
Apr
-
G. E. Moore, "Cramming more components onto integrated circuits," Electronics, vol. 38, no. 8, pp. 114-117, Apr. 1965.
-
(1965)
Electronics
, vol.38
, Issue.8
, pp. 114-117
-
-
Moore, G.E.1
-
2
-
-
35148845340
-
-
International Technology Roadmap for Semiconductors, Online, Available
-
International Technology Roadmap for Semiconductors. (2006). [Online]. Available: http://www.itrs.net/
-
(2006)
-
-
-
3
-
-
11144354892
-
A logic technology featuring strained-silicon
-
Apr
-
S. E. Thompson, M. Armstrong, C. Auth, S. Cea, R. Chau, G. Glass, T. Hoffman, J. Klaus, Z. Ma, B. Mcintrye, A. Murthy, B. Obradovic, L. Shifren, S. Sivakumar, S. Tyagi, T. Ghani, K. Mistry, M. Bohr, and Y. El-Mansy, "A logic technology featuring strained-silicon," IEEE Electron Device Lett., vol. 25, no. 4, pp. 191-193, Apr. 2004.
-
(2004)
IEEE Electron Device Lett
, vol.25
, Issue.4
, pp. 191-193
-
-
Thompson, S.E.1
Armstrong, M.2
Auth, C.3
Cea, S.4
Chau, R.5
Glass, G.6
Hoffman, T.7
Klaus, J.8
Ma, Z.9
Mcintrye, B.10
Murthy, A.11
Obradovic, B.12
Shifren, L.13
Sivakumar, S.14
Tyagi, S.15
Ghani, T.16
Mistry, K.17
Bohr, M.18
El-Mansy, Y.19
-
4
-
-
34247235178
-
Enhancing CMOS transistor performance using lattice-mismatched materials in source/drain regions
-
Jan
-
Y-C. Yeo, "Enhancing CMOS transistor performance using lattice-mismatched materials in source/drain regions," Semicond. Sci. Technol., vol. 22, no. 1, pp. S177-S182, Jan. 2007.
-
(2007)
Semicond. Sci. Technol
, vol.22
, Issue.1
-
-
Yeo, Y.-C.1
-
5
-
-
33847757121
-
High performance 35 nm LGATE CMOS transistors featuring NiSi metal gate (FUSI), uniaxial strained silicon channels and 1.2 nm gate oxide
-
P. Ranade, T. Ghani, K. Kuhn, K. Mistry, S. Pae, L. Shifren, M. Stettler, K. Tone, S. Tyagi, and M. Bohr, "High performance 35 nm LGATE CMOS transistors featuring NiSi metal gate (FUSI), uniaxial strained silicon channels and 1.2 nm gate oxide," in IEDM Tech. Dig., 2005, pp. 227-230.
-
(2005)
IEDM Tech. Dig
, pp. 227-230
-
-
Ranade, P.1
Ghani, T.2
Kuhn, K.3
Mistry, K.4
Pae, S.5
Shifren, L.6
Stettler, M.7
Tone, K.8
Tyagi, S.9
Bohr, M.10
-
6
-
-
33748100821
-
High performance gate first HfSiON dielectric satisfying 45 nm node requirements
-
M. A. Quevedo-Lopez, S. A. Krishnan, P. D. Kirsch, H. J. Li, J. H. Sim, C. Huffman, J. J. Peterson, B. H. Lee, G. Pant, B. E. Gnade, M. J. Kim, R. M. Wallace, D. Guo, H. Bu, and T. P. Ma, "High performance gate first HfSiON dielectric satisfying 45 nm node requirements," in IEDM Tech. Dig., 2005, pp. 437-440.
-
(2005)
IEDM Tech. Dig
, pp. 437-440
-
-
Quevedo-Lopez, M.A.1
Krishnan, S.A.2
Kirsch, P.D.3
Li, H.J.4
Sim, J.H.5
Huffman, C.6
Peterson, J.J.7
Lee, B.H.8
Pant, G.9
Gnade, B.E.10
Kim, M.J.11
Wallace, R.M.12
Guo, D.13
Bu, H.14
Ma, T.P.15
-
7
-
-
0842309728
-
Device physics at the scaling limit: What matters?
-
M. Lundstrom, "Device physics at the scaling limit: What matters?" in IEDM Tech. Dig., 2004, pp. 789-792.
-
(2004)
IEDM Tech. Dig
, pp. 789-792
-
-
Lundstrom, M.1
-
8
-
-
33646900503
-
Device scaling limits of Si MOSFETs and their application dependencies
-
Mar
-
D. J. Frank, R. H. Robert, E. Nowak, P. M. Solomon, Y. Taur, and H.-S. P. Wong, "Device scaling limits of Si MOSFETs and their application dependencies," Proc. IEEE, vol. 89, no. 3, pp. 259-288, Mar. 2001.
-
(2001)
Proc. IEEE
, vol.89
, Issue.3
, pp. 259-288
-
-
Frank, D.J.1
Robert, R.H.2
Nowak, E.3
Solomon, P.M.4
Taur, Y.5
Wong, H.-S.P.6
-
10
-
-
21644469564
-
80 nm self-aligned complementary I-MOS using double sidewall spacer and elevated drain structure and its applicability to amplifiers with high linearity
-
W. Y. Choi, J. Y. Song, B. Y. Choi, J. D. Lee, Y. J. Park, and B. G. Park, "80 nm self-aligned complementary I-MOS using double sidewall spacer and elevated drain structure and its applicability to amplifiers with high linearity," in IEDM Tech. Dig., 2004, pp. 203-206.
-
(2004)
IEDM Tech. Dig
, pp. 203-206
-
-
Choi, W.Y.1
Song, J.Y.2
Choi, B.Y.3
Lee, J.D.4
Park, Y.J.5
Park, B.G.6
-
11
-
-
33947220040
-
A novel CMOS-compatible L-shaped impact-ionization MOS (LI-MOS) transistor
-
E.-H. Toh, G. Wang, G.-Q. Lo, N. Balasubramanian, C.-H. Tung, F. Benistant, L. Chan, G. Samudra, and Y.-C. Yeo, "A novel CMOS-compatible L-shaped impact-ionization MOS (LI-MOS) transistor," in IEDM Tech. Dig., 2005, pp. 971-974.
-
(2005)
IEDM Tech. Dig
, pp. 971-974
-
-
Toh, E.-H.1
Wang, G.2
Lo, G.-Q.3
Balasubramanian, N.4
Tung, C.-H.5
Benistant, F.6
Chan, L.7
Samudra, G.8
Yeo, Y.-C.9
-
12
-
-
33847753444
-
70-nm impact-ionization metal-oxide-semiconductor (I-MOS) devices integrated with tunneling field-effect transistors (TFETs)
-
W. Y. Choi, J. Y. Song, B. Y. Choi, J. D. Lee, Y. J. Park, and B. G. Park, "70-nm impact-ionization metal-oxide-semiconductor (I-MOS) devices integrated with tunneling field-effect transistors (TFETs)" in IEDM Tech. Dig., 2005, pp. 975-978.
-
(2005)
IEDM Tech. Dig
, pp. 975-978
-
-
Choi, W.Y.1
Song, J.Y.2
Choi, B.Y.3
Lee, J.D.4
Park, Y.J.5
Park, B.G.6
-
13
-
-
35148899882
-
High current drive in ultra-short impact ionization MOS (I-MOS) devices
-
C. Charbuilet, S. Monfray, E. Dubois, P. Bouillon, F. Judong, and T. Skotnick, "High current drive in ultra-short impact ionization MOS (I-MOS) devices," in IEDM Tech. Dig., 2006, pp. 153-156.
-
(2006)
IEDM Tech. Dig
, pp. 153-156
-
-
Charbuilet, C.1
Monfray, S.2
Dubois, E.3
Bouillon, P.4
Judong, F.5
Skotnick, T.6
-
15
-
-
84990033752
-
Breakdown phenomenon in semiconductor and semiconductor devices
-
M. E. Levinshtein, J. Kostamovaara, and S. Vainshtein, "Breakdown phenomenon in semiconductor and semiconductor devices," Int. J. High Speed Electron. Syst., vol. 14, pp. 921-939, 2004.
-
(2004)
Int. J. High Speed Electron. Syst
, vol.14
, pp. 921-939
-
-
Levinshtein, M.E.1
Kostamovaara, J.2
Vainshtein, S.3
-
16
-
-
0001553399
-
Understanding hot-electron transport in silicon devices: Is there a shortcut?
-
Jul
-
M. V. Fischetti, S. E. Laux, and E. Crabbe, "Understanding hot-electron transport in silicon devices: Is there a shortcut?" J. Appl. Phys. vol. 78, no. 2, pp. 1058-1087, Jul. 1995.
-
(1995)
J. Appl. Phys
, vol.78
, Issue.2
, pp. 1058-1087
-
-
Fischetti, M.V.1
Laux, S.E.2
Crabbe, E.3
-
17
-
-
1942489095
-
Enhanced carrier velocity to early impact ionization
-
Apr
-
P. J. Hambleton, J. P. R. David, and G. J. Rees, "Enhanced carrier velocity to early impact ionization," J. Appl. Phys., vol. 95, no. 7, pp. 3561-3564, Apr. 2004.
-
(2004)
J. Appl. Phys
, vol.95
, Issue.7
, pp. 3561-3564
-
-
Hambleton, P.J.1
David, J.P.R.2
Rees, G.J.3
-
19
-
-
36449003566
-
Valence energy-band structure for strained group IV semiconductor
-
Feb
-
T. Manku and A. Nathan, "Valence energy-band structure for strained group IV semiconductor," J. Appl. Phys., vol. 73, no. 3, pp. 1205-1213, Feb. 1993.
-
(1993)
J. Appl. Phys
, vol.73
, Issue.3
, pp. 1205-1213
-
-
Manku, T.1
Nathan, A.2
-
20
-
-
34047195933
-
Strained-silicon transistors with silicon carbon source/ drain
-
Yokohama, Japan, Sep. 13-15
-
Y-C. Yeo, "Strained-silicon transistors with silicon carbon source/ drain," in Proc. Extended Abstracts Int. Conf. Solid State Devices Mater., Yokohama, Japan, Sep. 13-15, 2006, pp. 162-163.
-
(2006)
Proc. Extended Abstracts Int. Conf. Solid State Devices Mater
, pp. 162-163
-
-
Yeo, Y.-C.1
-
21
-
-
35148896095
-
-
FLOOPS version 10.0, Mountain View, CA: Synopsys-ISE
-
FLOOPS version 10.0, Mountain View, CA: Synopsys-ISE.
-
-
-
-
22
-
-
36449001067
-
Carbon incorporation in silicon for suppressing interstitial enhanced boron diffusion
-
Mar
-
P. A. Stolk, D. J. Eaglesham, H.-J. Gossmann, and J. M. Poate, "Carbon incorporation in silicon for suppressing interstitial enhanced boron diffusion," Appl. Phys. Lett., vol. 66, no. 11, pp. 1370-1372, Mar. 1995.
-
(1995)
Appl. Phys. Lett
, vol.66
, Issue.11
, pp. 1370-1372
-
-
Stolk, P.A.1
Eaglesham, D.J.2
Gossmann, H.-J.3
Poate, J.M.4
-
23
-
-
3242671509
-
A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors
-
T. Ghani, M. Armstrong, C. Auth, M. Bost, P. Charvat, G. Glass, T. Hoffmann, K. Johnson, C. Kenyon, J. Klaus, B. McIntyre, K. Mistry, A. Murthy, J. Sandford, M. Silberstein, S. Sivakumar, P. Smith, K. Zawadzki, S. Thompson, and M. Bohr, "A 90 nm high volume manufacturing logic technology featuring novel 45 nm gate length strained silicon CMOS transistors," in IEDM Tech. Dig., 2003, pp. 978-980.
-
(2003)
IEDM Tech. Dig
, pp. 978-980
-
-
Ghani, T.1
Armstrong, M.2
Auth, C.3
Bost, M.4
Charvat, P.5
Glass, G.6
Hoffmann, T.7
Johnson, K.8
Kenyon, C.9
Klaus, J.10
McIntyre, B.11
Mistry, K.12
Murthy, A.13
Sandford, J.14
Silberstein, M.15
Sivakumar, S.16
Smith, P.17
Zawadzki, K.18
Thompson, S.19
Bohr, M.20
more..
-
25
-
-
36449003027
-
x epitaxial layers
-
Feb
-
x epitaxial layers," Appl. Phys. Lett., vol. 62, no. 6, pp. 612-614, Feb. 1993.
-
(1993)
Appl. Phys. Lett
, vol.62
, Issue.6
, pp. 612-614
-
-
Kuo, P.1
Hoyt, J.L.2
Gibbons, J.F.3
Turner, J.E.4
Jacowitz, R.D.5
Kamins, T.I.6
-
26
-
-
0842288292
-
Process-strained Si (PSS) CMOS technology featuring 3D strain engineering
-
C.-H. Ge, C.-C. Lin, C.-H. Ko, C.-C. Huang, Y.-C. Huang, B.-W. Chan, B.-C. Perng, C.-C. Sheu, P.-Y. Tsai, L.-G. Yao, C.-L. Wu, T.-L. Lee, C.-J. Chen, C.-T. Wang, S.-C. Lin, Y.-C. Yeo, and C. Hu, "Process-strained Si (PSS) CMOS technology featuring 3D strain engineering," in IEDM Tech. Dig., 2003, pp. 73-76.
-
(2003)
IEDM Tech. Dig
, pp. 73-76
-
-
Ge, C.-H.1
Lin, C.-C.2
Ko, C.-H.3
Huang, C.-C.4
Huang, Y.-C.5
Chan, B.-W.6
Perng, B.-C.7
Sheu, C.-C.8
Tsai, P.-Y.9
Yao, L.-G.10
Wu, C.-L.11
Lee, T.-L.12
Chen, C.-J.13
Wang, C.-T.14
Lin, S.-C.15
Yeo, Y.-C.16
Hu, C.17
-
27
-
-
31844432924
-
200 mm germanium-on-insulator (GeOI) structures realized from epitaxial wafers using the smart cut(TM) technology
-
C. Deguet, J. Dechamp, C. Morales, A. Charvet, L. Clavelier, V. Loup, J. Hartmann, N. Kernevez, Y. Campidelli, F. Allibert, C. Richtarch, T. Akatsu, and F. Letertre, "200 mm germanium-on-insulator (GeOI) structures realized from epitaxial wafers using the smart cut(TM) technology," in Proc. Electrochem. Soc. Meetings, 2005, p. 78.
-
(2005)
Proc. Electrochem. Soc. Meetings
, pp. 78
-
-
Deguet, C.1
Dechamp, J.2
Morales, C.3
Charvet, A.4
Clavelier, L.5
Loup, V.6
Hartmann, J.7
Kernevez, N.8
Campidelli, Y.9
Allibert, F.10
Richtarch, C.11
Akatsu, T.12
Letertre, F.13
-
28
-
-
33646228663
-
A new strained-SOI/GOI dual CMOS technology based on local condensation technique
-
T. Tezuka, S. Nakaharai, Y. Moriyama, N. Hirashita, E. Toyoda, N. Sugiyama, T. Mizuno, and S. Takagi, "A new strained-SOI/GOI dual CMOS technology based on local condensation technique," in Proc. Symp. VLSI Technol., 2005, pp. 80-81.
-
(2005)
Proc. Symp. VLSI Technol
, pp. 80-81
-
-
Tezuka, T.1
Nakaharai, S.2
Moriyama, Y.3
Hirashita, N.4
Toyoda, E.5
Sugiyama, N.6
Mizuno, T.7
Takagi, S.8
-
29
-
-
4444251232
-
Direct-band-gap absorption in germanium under pressure
-
Jun
-
A. R. Goi, K. Syassen, and M. Cardona, "Direct-band-gap absorption in germanium under pressure," Phys. Rev. B, Condens. Matter, vol. 39, no. 17, pp. 921-924, Jun. 1989.
-
(1989)
Phys. Rev. B, Condens. Matter
, vol.39
, Issue.17
, pp. 921-924
-
-
Goi, A.R.1
Syassen, K.2
Cardona, M.3
|