Radiation-induced soft errors: A Chip-level modeling perspective

Foundations and Trends in Electronic Design Automation

Volumn 4, Issue 2-3, 2010, Pages 99-221

  Seifert, Norbert ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BULK CMOS; CHIP-LEVEL; EXPERIMENTAL MEASUREMENTS; PRODUCT-DESIGN CYCLES; RADIATION-INDUCED; SIMULATION-BASED; SOFT ERROR; SOFT ERROR RATE; SOFT ERROR RATE ESTIMATIONS; TWO SOURCES;

CMOS INTEGRATED CIRCUITS; ERROR CORRECTION; MICROPROCESSOR CHIPS;

PRODUCT DESIGN;

EID: 78650044288     PISSN: 15513939     EISSN: 15513947     Source Type: Journal    
DOI: 10.1561/1000000018     Document Type: Article

References (155)

1. S. Agostinelli et al., "GEANT4 - a simulation toolkit," Nuclear Instruments and Methods in Physics Research Section A, vol. 506, no. 3, pp. 250-303, available online at: http://cern.ch/geant4, 2003.
2. O. A. Amusan, private communication; runtime is estimated to equal about 72 hours per particle strike for a full 3D mixed-mode device simulation.
3. O. A. Amusan, A. L. Sternberg, A. F. Witulski, B. L. Bhuva, J. D. Black, M. P. Baze, and L. W. Massengill, "Single Event upsets in a 130nm hardened latch design due to charge sharing," in Proceedings of the International Reliability Physics Symposium (IRPS), pp. 306-311, 2007.
4. S. Baeg, P. Reviriego, J. Antonio Maestro, S. Wen, and R. Wong, "Analysis of a multiple cell upset failure model for memories," in IEEE Workshop on Silicon Errors in Logic - System Effects, Stanford University, March 24th and 25th 2009. A copy of the paper is available at: http://softerrors. info/selse/images/selse 2009/Papers/selse5 submission 7.pdf.
5. J. Baggio, D. Lambert, V. Ferlet-Cavrois, P. Paillet, C. Marcandella, and O. Duhamel, "Single event upsets induced by 1-10 MeV neutrons in static- RAMs using mono-energetic neutron sources," IEEE Transactions on Nuclear Science, vol. 54, no. 6, pp. 2149-2155, 2007.
6. J. Barak, R. A. Reed, and K. A. LaBel, "On the figure of merit model for SEU rate calculations," IEEE Transactions on Nuclear Science, vol. 46, no. 6, pp. 1504-1510, 1999.
7. R. Baumann, T. Hossain, S. Murata, and H. Kitagawa, "Boron compounds as a dominant source of alpha particles in semiconductor devices," in Proceedings of the 33rd Int'l Reliability Physics Symp. (IRPS), IEEE EDS, pp. 297-302, 1995.
8. R. C. Baumann, IEEE International Test Conference (ITC) 2005 SER Tutorial.
9. R. C. Baumann, "Radiation-induced soft errors in advanced semiconductor technologies," IEEE Transactions on Device and Materials Reliability, vol. 5, no. 3, pp. 305-316, 2005.
10. R. C. Baumann and D. Radaelli, "Determination of geometry and absorption effects and their impact on the accuracy of alpha particle soft error rate extrapolations," IEEE Transactions on Nuclear Science, vol. 54, no. 6, pp. 2141-2148, 2007.
11. R. C. Baumann and E. B. Smith, "Neutron-induced 10B fission as a major source of soft errors in high density SRAMs," Elsevier Microelectronics Reliability, vol. 41, no. 2, pp. 211-218, 2001.
12. M. P. Baze and S. P. Buchner, "Attenuation of single event induced pulses in cmos combinational logic," IEEE Transactions on Nuclear Science, vol. 44, no. 6, pp. 2217-2223, 1997.
13. M. J. Bellido-Diaz et al., "Logical modelling of delay degradation effect in static CMOS gates," IEEE Proceedings-Circuits Devices Systems, vol. 147, no. 2, pp. 107-111, 2000.
14. A. Biswas, P. Racunas, R. Cheveresan, J. Emer, S. S. Mukherjee, and R. Rangan, "Computing architectural vulnerability factors for address-based structures," in Proceedings of the IEEE International Symposium on Computer Architecture (ISCA), pp. 532-543, 2005.
15. A. Biswas, C. Recchia, S. S. Mukherjee, V. Ambrose, L. Chan, A. Jaleel, A. E. Papathanasiou, M. Plaster, and N. Seifert, "Explaining cache SER anomaly using DUE AVF measurement," in Proceedings of the High-Performance Computer Architecture, pp. 1-12, HPCA; Bangalore, India, 2010.
16. D. C. Bossen, A. Kitamorn, K. F. Reick, and M. S. Floyd, "Fault-tolerant design of the IBM pSeries 690 system using POWER4 processor technology," IBM Journal of Research and Development, vol. 46, no. 1, p. 77, 2002.
17. P. D. Bradley and E. Normand, "Single event upsets in implantable cardioverter defibrillators," IEEE Transactions on Nuclear Science, vol. 45, p. 2929, 1998.
18. E. H. Cannon, D. D. Reinhardt, M. S. Gordon, and P. S. Makowenskyj, "Multibit upsets in 65nm SOI SRAMs," in Proceedings of the Int'l Reliability Physics Symposium (IRPS), pp. 195-201, 2008.
19. E. H. Cannon et al., "SRAM SER in 90, 130, and 180nm bulk and SOI technologies," in Proceedings of the Int'l Reliability Physics Symposium (IRPS), pp. 300-304, 2004.
20. H. Cha, E. M. Rudnick, G. S. Choi, J. H. Patel, and R. K. Iyer, "A fast and accurate gate-level transient fault simulation environment," in The Twenty- Third International Symposium on Fault-Tolerant Computing, 1993. FTCS- 23. Digest of Papers, pp. 310-319, 1993.
21. B. Clark, "Alpha radiation sources in low alpha materials: Pb free materials. Refining and alpha flux reduction," Peaks in packaging 2003 (SEMITOOL).
22. B. M. Clark, M. W. Weiser, and I. J. Rasiah, "Alpha radiation sources in low alpha materials and implications for low alpha materials refinement," Thin Solid Films, vol. 462-463, pp. 384-386, 2004.
23. C. Dai, N. Hakim, S. Hareland, J. Maiz, and S.-W. Lee, "Alpha-SER modeling & simulation for sub-0.25 μm CMOS technology," Symposium on VLSI Technology, pp. 81-82, 1999.
24. C. Dai, N. Hakim, S. Walstra, S. Hareland, J. Maiz, S. Yu, and S.-W. Lee, "Neutron-SER modeling & simulation for 0.18 μm CMOS technology," SISPAD 2001, pp. 278-283, 2001.
25. A. Dixit, R. Heald, and A. Wood, "Trends from ten years of soft error experimentation," IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE 5, Stanford University, March 24 and 25, 2009); A copy of the paper is available at: http://www.selse.org, 2009.
26. P. E. Dodd, "Physics-based simulation of single-event effects," IEEE Transactions on Device and Materials Reliability, vol. 5, no. 3, pp. 343-357, 2005.
27. P. E. Dodd, M. R. Shaneyfelt, D. S. Walsh, J. R. Schwank, G. L. Hash, R. A. Loemker, B. L. Draper, and P. S. Winokur, "Single-event upset and snapback in Silicon-on-insulator devices and integrated circuits," IEEE Transactions on Nuclear Science, vol. 47, no. 6, pp. 2165-2173, 2000.
28. A. Fasso, A. Ferrari, and P. R. Sala, "Electron-photon transport in FLUKA: status," in Proceedings of Monte Carlo 2000 Conference, pp. 159-164, Lisbon, 2001.
29. V. Ferlet-Cavrois, P. Paillet, D. McMorrow, N. Fel, J. Baggio, S. Girard, O. Duhamel, J. S. Melinger, M. Gaillardin, J. R. Schwank, P. E. Dodd, M. R. Shaneyfelt, and J. A. Felix, "New insights into single event transient propagation in chains of inverters - evidence for propagation-induced pulse broadening," IEEE Transactions on Nuclear Science, vol. 55, no. 6, pp. 2842- 2853, 2008.
30. L. B. Freeman, "Critical charge calculations for a bipolar SRAM array," IBM Journal of Research Development, vol. 40, no. 1, pp. 119-129, 1996.
31. M. J. Gadlage, P. H. Eaton, J. M. Benedetto, , and T. L. Turflinger, "Comparison of heavy ion and proton induced combinatorial and sequential logic error rates in a deep submicron process," IEEE Transactions on Nuclear Science, vol. 52, no. 6, pp. 2120-2124, 2005.
32. M. J. Gadlage, P. H. Eaton, J. M. Benedetto, M. Carts, V. Zhu, and T. L. Turflinger, "Digital device error rate trends in advanced CMOS technologies," IEEE Transactions on Nuclear Science, vol. 53, no. 6, pp. 3466-3471, 2006.
33. G. Gasiot, D. Giot, and P. Roche, "Multiple cell upsets as the key contribution to the total SER of 65nm CMOS SRAMs and its dependence on well engineering," IEEE Transactions on Nuclear Science, vol. 54, no. 6, Part 1, pp. 2468-2473, 2007.
34. G. Gasiot, P. Roche, and P. Flatresse, "Comparison of multiple cell upset response of bulk and SOI 130nm technologies in the terrestrial environment," in Proceedings of Int'l Reliability Physics Symposium (IRPS), pp. 192-194, 2008.
35. B. Gill, N. Seifert, and V. Zia, "Comparison of alpha-particle and neutroninduced combinational and sequential logic error rates at the 32nm technology node," in Proceedings of the IEEE International Reliability Physics Symposium (IRPS), pp. 199-205, 2009.
36. B. S. Gill, C. Papachristou, F. G.Wolff, and N. Seifert, "Node sensitivity analysis for soft errors in CMOS logic," in Proceedings of the IEEE International Test Conference, pp. 964-972, 2005.
37. P. Goldhagen, private communication (e-mail sent on August 29, 2005).
38. M. S. Gordon, P. Goldhagen, K. P. Rodbell, T. H. Zabel, H. H. K. Tang, J. M. Clem, and P. Bailey, "Measurement of the flux and energy spectrum of cosmic-ray induced neutrons on the ground," IEEE Transactions on Nuclear Science, vol. 51, no. 6, pp. 3427-3434, 2004.
39. T. Granlund, B. Granbom, and N. Olsson, "A comparative study between two neutron facilities regarding SEU," IEEE Transactions on Nuclear Science, vol. 51, no. 5, pp. 2922-2926, 2004.
40. R. N. Hamm, J. E. Turner, H. A. Wright, and R. H. Ritchie, "Heavyion track structure in silicon," IEEE Transactions on Nuclear Science, vol. 26, no. 6, pp. 4892-4895, December 1979.
41. S. Hareland, J. Maiz, M. Alavi, K. Mistry, S. Walstra, and C. Dai, "Impact of CMOS process scaling and SOI on the soft error rates of logic processes," Digest of Technical Papers of the Symposium on VLSI Technology, pp. 73-74, 2001.
42. P. Hazucha, T. Karnik, J. Maiz, S. Walstra, B. Bloechel, J. Tschanz, G. Dermer, S. Hareland, P. Armstrong, and S. Borkar, "Neutron soft error rate measurements in a 90-nm CMOS process and scaling trends in SRAM from 0.25 μm to 90 nm generation," Electron Devices Meeting (IEDM) Technical Digest, pp. 21.5.1-21.5.4, 8-10 December 2003.
43. P. Hazucha, T. Karnik, S. Walstra, B. Bloechel, J. Tschanz, J. Maiz, K. Soumyanath, G. Demer, S. Narendra, V. De, and S. Borkar, "Measurements and analysis of SER tolerant latch in a 90-nm dual-Vt CMOS process," IEEE Custom Integrated Circuits Conference, pp. 617-620, 2003.
44. P. Hazucha, T. Karnik, S. Walstra, B. A. Bloechel, J. W. Tschanz, J. Maiz, K. Soumyanath, G. E. Dermer, S. Narendra, V. De, and S. Borkar, "Measurements and analysis of SER-tolerant latch in a 90-nm dual-Vt CMOS process," IEEE Journal of Solid-State Circuits, vol. 39, no. 9, pp. 1536-1543, September 2004.
45. P. Hazucha and C. Svensson, "Impact of CMOS technology scaling on the atmospheric neutron soft error rate," IEEE Transactions on Nuclear Science, vol. 47, no. 6, pp. 2586-2594, 2000.
46. A. E. Hedin, "Extension of the MSIS thermospheric model into the middle and lower atmosphere," Journal of Geophysical Research, vol. 96, p. 1159, 1991.
47. T. Heijmen, P. Roche, G. Gasiot, K. Forbes, and D. Giot, "A comprehensive study on the soft-error rate of flip-flops from 90-nm production libraries," IEEE Transactions on Device and Materials Reliability, vol. 7, no. 1, pp. 84-96, 2007.
48. J. S. Hendricks et al. MCNPX, version 2.5.e; MCNPX is a general-purpose Monte Carlo radiation transport code owned by the Los Alamos National Lab; see https://mcnpx.lanl.gov/, 2004.
49. D. M. Hiemstra, S. Yu, and M. Pop, "Single event characterization of the Pentium 4, Pentium III, and low power pentium MMX microprocessors usingproton irradiation," Proceedings of the IEEE Radiation Effects Data Workshop, pp. 51-57, 2002.
50. M. A. Horowitz, "Timing models For CMOS circuits," Technical Report SEL83-003, Integrated Circuits Laboratory, Stanford University, 1983.
51. L. Hsiao-Heng, K. Lilja, M. Bounasser, P. Relangi, I. R. Linscot, U. S. Inan, and S. Mitra, "LEAP: Layout design through error-aware transistor positioning for soft-error resilient sequential cell design," in Proceedings of the IEEE International Reliability Physics Symposium (IRPS), pp. 203-212, 2010.
52. G. Hubert, A. Bougerol, F. Miller, N. Buard, L. Anghel, T. Carriere, F. Wrobel, and R. Gaillard, "Prediction of transient induced by neutron/ proton in CMOS combinational logic cells," IEEE International On-Line Testing Symposium, IOLTS, pp. 63-74, 2006.
53. G. Hubert, J.-M. Palau, K. Castellani-Coulie, M.-C. Calvet, and S. Fourtine, "Detailed analysis of secondary ions' effect for the calculation of neutroninduced SER in SRAMs," IEEE Transactions on Nuclear Science, vol. 48, no. 6, Part 1, pp. 1953-1959, 2001.
54. E. Ibe, S. Chung, S. Wen, H. Yamaguchi, Y. Yahagi, H. Kameyama, S. Yamamoto, and T. Akioka, "Spreading diversity in multi-cell neutroninduced upsets with device scaling," in Proceedings of the IEEE Custom Integrated Circuits Conference (CICC), pp. 437-444, 2006.
55. E. Ibe, H. Taniguchi, Y. Yahagi, K. Shimbo, and T. Toba, "Impact of scaling on neutron-induced soft error in SRAMs From a 250nm to a 22 nm design rule," IEEE Transactions on Elect́ron Devices, vol. 57, no. 7, pp. 1527-1538, 2010.
56. "Measurement and reporting of alpha particle and terrestrial cosmic rayinduced soft errors in semiconductor devices," JEDEC Test Standard No. 89A, September 2006.
57. A. H. Johnston, "The influence of VLSI technology evolution on radiationinduced latchup in space systems," IEEE Transactions on Nuclear Science, vol. 43, no. 2, pp. 505-521, 1996.
58. Y. Kawakami, M. Hane, H. Nakamura, T. Yamada, and K. Kumagai, "Investigation of soft error rate including multi-bit upsets in advanced SRAM using neutron irradiation test and 3D mixed-mode device simulation," IEEE International Technical Digest Electron Devices Meeting (IEDM), p. 38.4.1, 2004.
59. A. J. KleinOsowski, P. Oldiges, R. Q. Williams, and P. M. Solomon, "Modeling single-event upsets in 65-nm silicon-on-insulator semiconductor devices," IEEE Transactions on Nuclear Science, vol. 53, no. 6, pp. 3321-3328, 2006.
60. H. Kobayashi, N. Kawamoto, J. Kase, and K. Shiraish, "Alpha particle and neutron-induced soft error rates and scaling trends in SRAM," in Proceedings of IEEE International Reliability Physics Symposium (IRPS), pp. 206-211, 2009.
61. S. Krishnaswamy, G. F. Viamontes, I. L. Markov, and J. P. Hayes, "Accurate reliability evaluation and enhancement via probabilistic transfer matrices," in Proceedings of Design, Automation and Test in Europe (DAT), vol. 1, pp. 282- 287, 2005.
62. D. Lambert, J. Baggio, V. Ferlet-Cavrois, O. Flament, F. Saigne, B. Sagnes, N. Buard, and T. Carriere, "Neutron-induced SEU in bulk SRAMs interrestrial environment: Simulations and experiments," IEEE Transactions on Nuclear Science, vol. 51, no. 6, pp. 3435-3441, December 2004.
63. D. Lambert, J. Baggio, V. Ferlet-Cavrois, O. Flament, F. Saigne, B. Sagnes, N. Buard, and T. Carriere, "Neutron-induced SEU in SRAMs: Simulations with n-Su and n-O interactions," IEEE Transactions on Nuclear Science, vol. 52, no. 6, pp. 2332-2339, 2005.
64. E. D. Lazowska, J. Zahorjan, G. Scott Graham, and K. C. Sevcik, Quantitative System Performance. Prentice-Hall, Inc., Englewood Cliffs, New Jersey, 1984.
65. F. Lei, S. Clucas, C. Dyer, and P. Truscott, "An atmospheric radiation model based on response matrices generated by detailed Monte Carlo Simulations of cosmic ray interactions," IEEE Transactions on Nuclear Science, vol. 51, no. 6, Part 2, pp. 3442-3451, 2004.
66. J. R. Letaw and E. Normand, "Guidelines for predicting single-event upsets in neutron environments," IEEE Transactions on Nuclear Science, vol. 38, no. 6, pp. 1500-1506.
67. R. Leveugle, "Fault injection in VHDL descriptions and emulation," IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, pp. 414-419, 2000.
68. D. R. Lide, ed., Handbook of Chemistry and Physics. CRC Press, Boca Raton, FL, 73rd ed., pp. 11-115, 1972.
69. J. D. C. Little, "A proof for the queuing formula: L = λW," Operations Research, vol. 9, no. 3, pp. 383-387, 1961.
70. M. S. Lundstrom, "Fundamentals of carrier transport," vol. X, The Modular Series on Solid State Devices, Addison-Wesley, Reading, MA, 1990.
71. J. Maiz, S. Hareland, K. Zhang, and P. Armstrong, "Characterization of multibit soft error events in advanced SRAMs," International Electron Devices Meeting (IEDM), Technical Digest, pp. 21.4.1-21.4.4, 2003.
72. R. C. Martin, N. M. Ghoniem, Y. Song, and J. S. Cable, "The size effect of ion charge tracks on single event multiple-bit upset," IEEE Transactions on Nuclear Science, vol. 34, no. 6, pp. 1305-1309, 1987.
73. L. W. Massengill and P. W. Tuinenga, "Single-event transient pulse propagation in digital CMOS," IEEE Transactions on Nuclear Science, vol. 55, no. 6, Part 1, pp. 2861-2871, 2008.
74. D. G. Mavis and P. H. Eaton, "SEU and SET modeling and mitigation in deep submicron technologies," Proceedings of the IEEE International Reliability Physics Symposium, pp. 293-305, 2007.
75. K. G. McKay and K. B. McAfee, "Electron multiplication in silicon and germanium," Physical Review, vol. 91, pp. 1079-1084, 1953.
76. G. C. Messenger, "Collection of charge on junction nodes from ion tracks," IEEE Transactions on Nuclear Science, vol. NS-29, no. 6, pp. 2024-2031, 1982.
77. N. Miskov-Zivanov and D. Marculescu, "Circuit reliability analysis using symbolic techniques," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 12, pp. 2638-2649, 2006.
78. N. Miskov-Zivanov and D. Marculescu, "Modeling and optimization of softerror reliability of sequential circuits," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, no. 5, pp. 803-816, 2008.
79. K. Mistry et al., "A 45nm logic technology with high-k+metal gate transistors, strained silicon, 9 Cu interconnect layers, 193nm dry patterning, and 100% pb-free packaging," pp. 247-250, 2007.
80. S. Mitra, N. Seifert, M. Zhang, Q. Shi, and K. S. Kim, "Robust system design with built-in soft-error resilience," Computer, vol. 38, no. 2, pp. 43-52, 2005.
81. Moscow Neutron Monitor; http://helios.izmiran.rssi.ru/cosray/main.htm, One of many neutron monitors around the world that measure and post neutron flux statistics (current and archived) on the web.
82. K. Mohanram and N. A. Touba, "Cost-effective approach for reducing soft error failure rate in logic circuits," in Proceedings of ITC, pp. 893-901, 2003.
83. G. E. Moore, "Cramming more components onto integrated circuits," Electronics, vol. 38, no. 8, 19, pp. 114-117, 1965.
84. S. Mukherjee, Architecture Design for Soft Errors. Morgan-Kaufmann, February 2008.
85. S. S. Mukherjee, J. Emer, T. Fossum, and S. K. Reinhardt, "Cache scrubbing in microprocessors: myth or necessity?," in Proceedings of IEEE Pacific Rim International Symposium on Dependable Computing, pp. 37-42, 2004.
86. S. S. Mukherjee, C. Weaver, J. Emer, S. K. Reinhardt, and T. Austin, "A systematic methodology to compute the architectural vulnerability factors for a high-performance microprocessor," in 36th Annual International Symposium on Microarchitecture (MICRO), December 2003.
87. P. C. Murley and G. C. Srinivasan, "Soft-error Monte Carlo modeling program SEMM," IBM Journal of Research and Development, vol. 40, no. 1, pp. 109-118, 1996.
88. O. Musseau, V. Ferlet-Cavrois, A. B. Campbell, A. R. Knudson, S. Buchner, B. Fischer, and M. Schlogl, "Technique to measure an ion track profile," IEEE Transactions on Nuclear Science, vol. 45, no. 6, pp. 2563-2570, 1998.
89. B. Narasimham, "Characterization of heavy-ion, neutron and alpha particleinduced single-event transient pulse width in advanced CMOS technologies," PhD thesis, Vanderbilt University, Nashville, TN, USA, December 2008.
90. B. Narasimham, M. J. Gadlage, B. L. Bhuva, R. D. Schrimpf, L. W. Massengill, W. Timothy Holman, A. F. Witulski, X. Zhu, A. Balasubramanian, and S. A. Wender, "Neutron and alpha particle-induced transients in 90 nm technology," in Proceedings of the IEEE International Reliability Physics Symposium (IRPS), pp. 478-481, 2008.
91. H. T. Nguyen and Y. Yagil, "A systematic approach to SER estimation and solutions," in Proceedings of the IEEE International Reliability Physics Symposium (IRPS), pp. 60-70, 2003.
92. H. T. Nguyen, Y. Yagil, N. Seifert, and M. Reitsma, "Chip-level soft error estimation method," IEEE Transactions on Device and Materials Reliability, vol. 5, no. 3, pp. 365-381, September 2005.
93. M. Nicholaidis, "Design for soft error mitigation," IEEE Transactions on Device and Materials Reliability, vol. 5, no. 3, pp. 405-418, 2005.
94. E. Normand, "Single event effects in avionics," IEEE Transactions on Nuclear Science, vol. 43, pp. 461-474, 1996.
95. E. Normand, "Use of ENDF/B-VI proton and neutron cross sections for single event upset calculations," IEEE Transactions on Nuclear Science, vol. 46, p. 1386, 1999.
96. E. Normand, "Extension of the FOM method - proton SEL and atmospheric neutron SEU," IEEE Transactions on Nuclear Science, vol. 51, no. 6, Part 2, pp. 3494-3504, 2004.
97. E. Normand, "Extensions of the FOM method - proton SEL and atmospheric neutron SEU," IEEE Transactions on Nuclear Science, vol. 51, no. 6, pp. 3494-3504, 2004.
98. P. Oldiges, R. Dennard, D. Heidel, B. Klaasen, R. Assaderaghi, and M. Ieong, "Theoretical determination of the temporal and spatial structure of a-particle induced electron-hole pair generation in silicon," IEEE Transactions on Nuclear Science, vol. 47, no. 6, pp. 2575-2579, December 2000.
99. M. Olmos, R. Gaillard, A. Van Overberghe, J. Beaucour, S. Wen, and S. Chung, "Investigation of thermal neutron induced soft error rates in commercial srams with 0.35 μm to 90 nm technologies," International Physics Reliability Symposium, pp. 212-216, 2006.
100. M. Omana, G. Papasso, D. Rossi, and C. Metra, "Attenuation of single event induced pulses in CMOS combinational logic," in Proceedings of the 9th IEEE International Online Testing Symposium (IOLTS), pp. 111-115, 2003.
101. J. M. Palau, M. C. Calvet, P. E. Dodd, F. W. Sexton, and P. Roche, "Contribution of device simulation to SER understanding," in Proceedings of IEEE International Reliability Physics Symposium, pp. 71-75, 2003.
102. E. Petersen private communication.
103. E. L. Petersen, "The SEU figure of merit and proton upset rate calculations," IEEE Transactions on Nuclear Science, vol. 45, pp. 2550-2562, 1998.
104. PHITS (Particle and Heavy Ion Transport code System) http://phits. jaea.go.jp/.
105. S. Prejean, "Accelerated neutron soft error rate testing of AMD microprocessors," presented at the IEEE Workshop on Silicon Errors in Logic - System Effects (SELSE 6, Stanford University, March 24 and 25, 2009); Available online at: http://www.selse.org/.
106. D. Radaelli, H. Puchner, W. Skip, and S. Daniel, "Investigation of multi-bit upsets in a 150nm technology SRAM device," IEEE Transactions on Nuclear Science, vol. 52, no. 6, 2006.
107. T. V. Rajeevakumar, N. C. C. Lu, W. H. Henkels, W. Hwang, and R. Franch, "A new mode of radiation-induced soft errors in dynamic memories," IEEE Electron Device Letters, vol. 9, no. 12, pp. 644-646, 1988.
108. R. R. Rao, K. Chopra, D.Blaauw, and D. Sylvester, "An efficient static algorithm for computing the soft error rates of combinational circuits," in Proceedings of Design, Automation and Test in Europe (DATE), vol. 1, no. 6-10, pp. 1-6, 2006.
109. Robust Chip Inc. website: http://www.robustchip.com/.
110. K. Rodbell, D. Heidel, H. Tang, M. Gordon, P. Oldiges, and C. Murray, "Lowenergy proton-induced single-event-upsets in 65nm node, silicon on-insulator, latches and memory cells," IEEE Transactions on Nuclear Science, vol. 54, no. 6, pp. 2474-2479, December 2007.
111. F. X. Ruckerbauer and G. Georgakos, "Soft error rates in 65nm SRAMs - Analysis of new phenomena," Proceedings of the IEEE International On-Line Testing Symposium, pp. 203-204, 2007.
112. A. M. Saleh, J. J. Serrano, and J. H. Patel, "Reliability of scrubbing recoverytechniques for memory systems," IEEE Transactions on Reliability, vol. 39, no. 1, pp. 114-122, 1990.
113. P. N. Sanda, J. W. Kellington, P. Kudva, R. Kalla, R. B. McBeth, J. Ackaret, R. Lockwood, J. Schumann, and C. R. Jones, "Soft-error resilience of the IBM POWER6 processor," IBM Journal of Research and Development, vol. 52, no. 3, pp. 275-284, 2008.
114. N. Seifert, "Soft error rates of hardened sequentials utilizing local redundancy," invited talk, IEEE International On-line Testing Symposium, (Rhodes, Greece), pp. 49-50, 7-9 July 2008.
115. N. Seifert, "Radiation-induced soft error performance of deep submicron CMOS bulk devices," Invited talk given at the Single Event Effects Symposium (La Jolla, CA), 12-14 April 2010.
116. N. Seifert, V. Ambrose, B. Gill, Q. Shi, R. Allmon, C. Recchia, S. Mukherjee, N. Nassif, J. Krause, J. Pickholtz, and A. Balasubramanian, "On the radiationinduced soft error performance of hardened sequential elements in advanced bulk CMOS technologies," in Proceedings of the IEEE International Reliability Physics Symposium (IRPS), pp. 188-197, 2010.
117. N. Seifert, B. Gill, K. Foley, and P. Relangi, "Multi-cell upset probabilities of 45nm high-k + metal gate SRAM devices in terrestrial and space environments," in Proceedings of the IEEE International Reliability Physics Symposium (IRPS), pp. 181-186, 2008.
118. N. Seifert, B. Gill, V. Zia, M. Zhang, and V. Ambrose, "On the scalability of redundancy based SER mitigation schemes," in Proceedings of IEEE International Conference on Integrated Circuit Design and Technology (ICICDT), pp. 1-9, 2007.
119. N. Seifert, P. Shipley,M. D. Pant, V. Ambrose, and B. Gill, "Radiation induced clock jitter and race," in Proceedings of the IEEE International Reliability Physics Symposium, pp. 215-222, IRPS, San Jose, CA, April 2005.
120. N. Seifert, P. Slankard, M. Kirsch, B. Narasimham, V. Zia, C. Brookreson, A. Vo, S. Mitra, B. Gill, and J. Maiz, "Radiation-induced soft error rates of advanced CMOS bulk devices," in Proceedings of the IEEE International Physics Symposium, pp. 217-225, 2006.
121. N. Seifert and N. Tam, "Timing vulnerability factors of sequentials," IEEE Transactions on Device and Materials Reliability, vol. 4, no. 3, pp. 516-522, 2004.
122. N. Seifert, X. Zhu, and L. Massengill, "Impact of scaling on soft error rates in commercial microprocessors," IEEE Transactions on Nuclear Science, vol. 49, no. 5, pp. 3100-3106, 2002.
123. S. Selberherr, Analysis and Simulation of Semiconductor Devices. Springer Verlag, Vienna, 1984.
124. The Second Workshop on System Effects of Logic Soft Errors, University of Illinois at Urbana-Champaign, April 11th-12th, 2006. For recap/summary of SELSE 2 workshop, see: http://www.selse.org.
125. Sentaurus Advanced multidimensional (1D-3D) device simulator sold by Synopsys Inc.; .
126. P. Shivakumar, M. Kistler, S. W. Keckler, D. Burger, and L. Alvisi, "Modeling the effect of technology trends on the soft error rate of combinational logic," in Proceedings of the IEEE Dependable Systems and Networks Conference, pp. 389-398, June 2002.
127. The original SPICE simulator was developed at the University of California at Berkeley. SPICE is an acronym for "Simulation Program with Integrated Circuit Emphasis." For more information, please see http://www.eecs.berkeley.edu/.
128. Particle Interactions with Matter - The Stopping and Range of Ions in Matter, J. Ziegler; available online at : http://www.srim.org/.
129. R. V. T. Calin, M. Nicolaidis, "Upset hardened memory design for submicron CMOS technology," IEEE Transactions on Nuclear Science, vol. 43, no. 6, pp. 2874-2878, December 1996.
130. A. Taber and E. Normand, "Single event upset in avionics," IEEE Transactions on Nuclear Science, vol. 40, no. 2, pp. 120-126, 1993.
131. H. H. K. Tang and E. H. Cannon, "SEMM-2: A modeling system for single event upset analysis," IEEE Transactions on Nuclear Science, vol. 51, no. 6, pp. 3342-3348, 2004.
132. H. K. Tang, "Nuclear physics of cosmic ray interaction with semiconductor materials: Particle-induced soft errors from a physicist's perspective," IBM Journal of Research and Development, vol. 40, no. 1, pp. 91-108, 1996.
133. H. K. Tang and K. P. Rodbell, "Single-event upsets in microelectronics: Fundamental physics and issues," Material Research Society Bulletin, vol. 28, pp. 111-116, February 2003.
134. EDA tool developed and sold by iROC Technologies: http://www. iroctech.com/.
135. Y. Tosaka, H. Ehara, M. Igeta, T. Uemura, H. Oka, N. Matsuoka, and K. Hatanaka, "Comprehensive study of soft errors in advanced CMOS circuits with 90/130nm technology," IEEE International Electron Devices Meeting, IEDM Technical Digest, pp. 38.3.1-38.3.4, 2004.
136. Y. Tosaka, H. Kanata, T. Itakura, and S. Satoh, "Simulation technologies for cosmic ray neutron-induced soft errors: Models and simulation systems," IEEE Transactions on Nuclear Science, vol. 46, pp. 774-779, 1999.
137. Y. Tosaka, H. Kanata, S. Satoh, and T. Itakura, "Simple method for estimating neutron-induced soft error rates based on modified BGR model," IEEE Electron Device Letters, vol. 20, no. 2, pp. 89-91, 1999.
138. Y. Tosaka, R. Takasu, T. Uemura, H. Ehara, H. Matsuyama, S. Satoh, and A. Kawai, "Simultaneous measurement of soft error rate of 90nm CMOS SRAM and cosmic ray neutron spectra at the summit of Mauna Kea," in Proceedings of the IEEE International Reliability Physics Symposium (IRPS), pp. 727-728, 2008.
139. M. Turowski, A. Fedoseyev, A. Raman, and K. Warren, "Single event upset modeling with nuclear reactions in nanoscale electronics," International Conference on Mixed Design of Integrated Circuits and Systems, (MIXDES), pp. 443-448, 2008.
140. S. Walstra, unpublished.
141. S. V. Walstra and C. Dai, "Circuit-level modeling of soft errors in integrated circuits," IEEE Transactions on Device and Materials Reliability, vol. 5, no. 3, pp. 358-364, 2005.
142. F. Wang and Y. Xie, "Soft error rate analysis for combinational logic using an accurate electrical masking model," IEEE Transactions on Dependable and Secure Computing, 2007.
143. K. M. Warren, A. L. Sternberg, R. A. Weller, M. P. Baze, L. W. Massengill, R. A. Reed, M. H. Mendenhall, and R. D. Schrimpf, "Integrating circuit level simulation and Monte-Carlo radiation transport code for single event upset analysis in SEU hardened circuitry," IEEE Transactions on Nuclear Science, vol. 55, no. 6, Part 1, pp. 2886-2894, 2008.
144. K. M. Warren, R. A. Weller, B. D. Sierawski, R. A. Reed, M. H. Mendenhall, R. D. Schrimpf, L. W. Massengill, M. E. Porter, J. D. Wilkinson, K. A. Label, and J. H. Adams, "Application of RADSAFE to model the single event upset response of a 0.25 μm CMOS SRAM," IEEE Transactions on Nuclear Science, vol. 43, no. 4, Part 2, pp. 898-903, 2007.
145. S. Wen, R. Wong, M. Romain, and N. Tam, "Thermal neutron soft error rate for SRAMs in the 90 nm-45nm technology range," in Proceedings of IEEE International Reliability Physics Symposium (IRPS), pp. 1036-1039, 2010.
146. F. Wrobel, J. M. Palau, M. C. Calvet, O. Bersillon, and H. Duarte, "Incidence of multi-particle events on soft error rates caused by n-Si nuclear reactions," IEEE Transactions on Nuclear Science, vol. 47, pp. 2580-2585, December 2000.
147. Y. Yahagi, H. Yamaguchi, E. Ibe, H. Kameyama, M. Sato, T. Akioka, and S. Yamamoto, "Novel mechanism of neutron-induced multi-cell error in CMOS devices tracked down from 3D device simulations," in Simulation of Semiconductor Processes and Devices (SISPAD), pp. 184-187, 2006.
148. B. Zhang, W. S. Wang, and M. Orshansky, "FASER: Fast analysis of soft error susceptibility of cell-based designs," International Symposium on Quality Electronic Design (ISQED), 2006.
149. M. Zhang, S. Mitra, T. M. Mak, N. Seifert, N. J. Wang, Q. Shi, K. Sup Kim, N. R. Shanbhag, and S. J. Patel, "Sequential element design with built-in soft error resilience," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 14, no. 12, pp. 1368-1378, 2006.
150. M. Zhang and N. R. Shanbhag, "Soft-error-rate-analysis (SERA) methodology," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, no. 10, pp. 2140-2155, 2006.
151. J. F. Ziegler, "Terrestrial cosmic rays," IBM Journal of Research and Development, vol. 40, no. 1, pp. 19-39, 1996.
152. J. F. Ziegler, "Terrestrial cosmic ray intensities," IBM Journal of Research and Development, vol. 42, no. 1, pp. 117-139, 1998.
153. J. F. Ziegler, J. P. Biersack, and U. Littmark, The Stopping and Range of Ions in Solids. Pergamon Press, New York, 1985.
154. J. F. Ziegler and W. A. Lanford, "Effect of cosmic rays on computer memories," Science, vol. 206, no. 4420, pp. 776-788, 1979.
155. J. F. Ziegler and W. A. Lanford, "The effect of sea level cosmic rays on electronic devices," Journal of Applied Physics, vol. 52, pp. 4305-4318, 1981.