Soft error rates of radhard sequentials utilizing local redundancy

Proceedings - 14th IEEE International On-Line Testing Symposium, IOLTS 2008

Volumn , Issue , 2008, Pages 49-50

  Seifert, Norbert ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACTINIDES; CLOCKS; ELECTRIC NETWORK ANALYSIS; HARDENING; LEARNING SYSTEMS; MACHINE DESIGN; MECHANISMS; METALS; NANOTECHNOLOGY; NEUTRON IRRADIATION; NEUTRONS; QUALITY ASSURANCE; RADIATION HARDENING; RADIATION PROTECTION; REDUNDANCY; RELIABILITY; SEPARATION; TECHNOLOGY; WIRELESS TELECOMMUNICATION SYSTEMS;

CHARGE SHARING; CHIP-LEVEL; CLOCK TREE; COMBINATIONAL LOGICS; CRITICAL NODES; DATA PATTERNS; ERROR BLOCKING; LOS ALAMOS NATIONAL LABORATORY; METAL GATES; MITIGATION TECHNIQUES; ON-LINE TESTING; ORDERS-OF-MAGNITUDE; PARTICLE IRRADIATION; PROCESS SCALING; RADIATION-HARDENED; SEQUENTIAL DESIGNS; SINGLE-EVENT UPSET; SINGLE-EVENT UPSETS; SOFT ERROR RATES; SOFT ERRORS; STATIC FAILURES; UPSET RATES;

ERROR ANALYSIS;

EID: 52049108013     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IOLTS.2008.61     Document Type: Conference Paper

References (7)

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5. M. Zhang, et al., "Sequential Element Design With Built-In Soft Error Resilience," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Volume 14, Issue 12, Dec. 2006 Page(s):1368 - 1378.
6. K. Mistry, et al., "A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging", Technical Digest of the IEEE International Electron Devices Meeting, pp. 247-250, 2007
7. N. Seifert et al., "On the Scalability of Redundancy based SER Mitigation Schemes", Proceedings of IEEE International Conference on Integrated Circuit Design and Technology (ICICDT), pp. 1-9, 2007.