Upset hardened memory design for submicron CMOS technology

IEEE Transactions on Nuclear Science

Volumn 43, Issue 6 PART 1, 1996, Pages 2874-2878

  Calin T ^a   Nicolaidis, M ^a   Velazco, R ^a  

^a LSR IMAG Laboratory   (France)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; RADIATION EFFECTS; RADIATION HARDENING; RANDOM ACCESS STORAGE;

SINGLE EVENT UPSET (SEU) HARDENING;

CMOS INTEGRATED CIRCUITS;

EID: 0030375853     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/23.556880     Document Type: Article

References (12)

1. T. Ma, P. Dressendorfer, "Ionizing Radiation Effects in MOS Devices and Circuits," Wiley 1989.
2. S. E. Kerns, B. D. Shafer, eds, "The Design of RadiationHardened ICs for Space: A Compendium of Approaches," Proc. IEEE, Nov. 1988, pp. 1470-1509.
3. S. Yoshioka, H. Kamimura, M. Akiyama, "A RadiationHardened 32-bit Microprocessor Based on the Commercial CMOS Process," IEEE Trans. Nucl. Sei. , vol. 41, n° 6, Dec. 1994, pp. 24812486.
4. E. L. Petersen, P. Shapiro, J. H. Adams, Jr. , and E. A. Burke, "Calculations of Cosmic Ray Induced. Soft Upsets and Scaling in VLSI Devices," IEEE Trans, on Nuclear Science, vol. NS-29, n° 6, Dec. 1982, pp. 2055-2063.
5. J. Abraham, E. Davidson, J. Patel, "Memory System Design for Tolerating Single Event Upsets," IEEE Trans. Nucl. Sei. , vol. NS30, n° 6, Dec. 1983, pp. 4339-4344.
6. R. Johnson, S. Diehl, "An Improved SEU Resistive Hardening technique for CMOS Static RAMs," IEEE Trans. Nucl. Sei. , vol. NS-33, n° 6, Dec. 1986, pp. 1727-1733.
7. T. Câlin, F. L. Vargas, M. Nicolaidis, "Upset-Tolerant CMOS SRAM Using Current Monitoring: Prototype and Test Experiments," Proc. 1995 International Test Conference, pp. 45-53.
8. L. Rockett, "An SEU Hardened CMOS Data Latch Design", IEEE Trans. Nucl. Sei. , vol. NS-35, n° 6, Dec. 1988, pp. 1682-1687.
9. S. Whitaker, J. Canaris, K. Liu, "SEU Hardened Memory Cells for a CCSDS Reed Solomon Encoder," IEEE Transactions on Nuclear Science, vol. NS-38, n° 6, Dec. 1991, pp. 1471-1477.
10. D. Bessot, R. Velazco, "Design of SEU-Hardened CMOS Memory Cells: The HIT Cell," Proceedings 1993 RADECS Conference, pp. 563-570.
11. M. N. Liu, S. Whitaker, "Low Power SEU Immune CMOS Memory Circuits," IEEE Trans. Nucl. Sei. , vol. NS-39, n° 6, Dec. 1992, pp. 1679-1684.
12. R. Velazco, T. Câlin, M. Nicolaidis, S. C. Moss, S. D. La Lumondiere, V. T. Tran, R. Koga, "SEU-Hardened Storage Cell Validation Using A Pulsed Laser", in this issue of IEEE Trans. Nucl. Sei. , vol. NS-46, n° 6, Dec. 1996.