A 45nm logic technology with high-k+ metal gate transistors, strained silicon, 9 Cu interconnect layers, 193nm dry patterning, and 100% Pb-free packaging

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2007, Pages 247-250

  Mistry, K ^a   Allen, C ^a   Auth, C ^a   Beattie, B ^a   Bergstrom, D ^a   Bost, M ^a   Brazier, M ^a   Buehler, M ^a   Cappellani, A ^a   Chau, R ^a   Choi, C H ^a   Ding, G ^a   Fischer, K ^a   Ghani, T ^a   Grover, R ^a   Han, W ^a   Hanken, D ^a   Hattendorf, M ^a   He, J ^a   Hicks, J ^a   Huessner, R ^a   Ingerly, D ^a   Jain, P ^a   James, R ^a   Jong, L ^a   Joshi, S ^a   Kenyon, C ^a   Kuhn, K ^a   Lee, K ^a   Liu, H ^a   Maiz, J ^a   McIntyre, B ^a   Moon, P ^a   Neirynck, J ^a   Pae, S ^a   Parker, C ^a   Parsons, D ^a   Prasad, C ^a   Pipes, L ^a   Prince, M ^a   Rarade, P ^a   Reynolds, T ^a   Sandford, J ^a   Shifren, L ^a   Sebastian, J ^a   Seiple, J ^a   Simon, D ^a   Sivakumar, S ^a   Smith, P ^a   Thomas, C ^a   Troeger, T ^a   Vandervoorn, P ^a   Williams, S ^a   Zawadzki, K ^a   more..

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COPPER; CURING; DRYING; ELECTRON DEVICES; GATE DIELECTRICS; GATES (TRANSISTOR); INDUSTRIAL ENGINEERING; LEAD; LEAD ALLOYS; METALS; NONMETALS; OPTICAL INTERCONNECTS; SEMICONDUCTING SILICON COMPOUNDS; SILICON; TECHNOLOGY; TRANSISTORS;

45-NM LOGIC TECHNOLOGY; COPPER INTERCONNECTS; CU INTERCONNECTS; DRIVE CURRENTS; DRY PATTERNING; DUAL BANDS; HIGH VOLUME MANUFACTURING; HIGH-K GATE DIELECTRICS; LOCAL ROUTING; LOW COSTS; METAL GATE TRANSISTORS; METAL GATES; PB-FREE; PROCESS YIELD; SRAM ARRAYS; SRAM CELLS; STRAINED SILICON; THIRD GENERATION; WORK FUNCTIONS;

STATIC RANDOM ACCESS STORAGE;

EID: 50249185641     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2007.4418914     Document Type: Conference Paper

References (9)

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7. P. Bai et al., "A 65nm Logic Technology Featuring 35nm Gate Lengths, Enhanced Channel Strain, 8 Cu Interconnect Layers, Low-k ILD, and 0.57μm SRAM Cell" IEDM Tech. Dig., pp. 657-660, 2004.
8. S. Tyagi et al., "An advanced low power, high performance, strained channel 65nm technology," IEDM Tech. Dig., pp. 1070-1072, 2005.
9. H. Takeuchi et al., "Impact of Oxygen Vacancies on High-k Gate Stack Engineering" IEDM Tech. Dig., pp. 829-832, 2004.