Multi-bit upsets in 65nm SOI SRAMs

IEEE International Reliability Physics Symposium Proceedings

Volumn , Issue , 2008, Pages 195-201

  Cannon, Ethan H ^a   Gordon, Michael S ^b   Heidel, David F ^b   KleinOsowski, A J ^c   Oldiges, Phil ^d   Rodbell, Kenneth P ^b   Tang, Henry H K ^b  

^a IBM   (United States)

^b IBM T J WATSON RESEARCH CENTER   (United States)

^c IBM AUSTIN RESEARCH LABORATORY   (United States)

^d IBM RESEARCH   (United States)

Author keywords

Cosmic rays; Multi bit upset; Single event upset (SEU); Soft error rate (SER)

Indexed keywords

COSMIC RAYS; MULTI-BIT UPSET; RELIABILITY PHYSICS; SINGLE-EVENT UPSET (SEU); SOFT ERROR RATE (SER);

ACTINIDES; ERROR ANALYSIS;

STATIC RANDOM ACCESS STORAGE;

EID: 51549099436     PISSN: 15417026     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RELPHY.2008.4558885     Document Type: Conference Paper

References (24)

1. R. Baumann, "The Impact of Technology Scaling on Soft Error Rate Performance and Limits to the Efficacy of Error Correction," Intl Electron Devices Meeting (IEDM), pp. 329-332, 2002.
2. D. F. Heidel, K. P. Rodbell, P. Oldiges, M. S. Gordon, H. H. Tang, E. H. Cannon and C. Plettner, "Single-Event-Upset Critical Charge Measurements and Modeling of 65nm Latches and Memory Cells," IEEE Trans. Nuc. Sci., vol. 53, pp. 3512-3517, 2006.
3. T. Heijmen, P. Rocher, G. Gasiot, K. R. Forbes and D. Giot, "A Comparative Study on the Soft-Error Rate of Flip-Flops from 90-nm Production Libraries," IEEE Trans. Device and Materials Reliability, pp. 84-96, 2007.
4. F. Wrobel, J.-M. Palau, M.-C. Calvet, O. Bersillon and H. Duarte, "Simulation of Nucleon-Induced Nuclear Reactions in a Simplified SRAM Structure: Scaling Effects on SEU and MBU Cross Sections" IEEE Trans. Nuc. Sci., vol. 48, pp. 1946-1952, 2001.
5. O. A. Amusan, et al., "Charge Collection and Charge Sharing in a 130 nm CMOS Technology," IEEE Trans. Nuc Sci., vol. 53, pp. 3253-3258, 2006.
6. G. Gasiot, D. Giot and P. Roche, "Multiple Cell Upsets as the Key Contribution to the Total SER of 65 nm CMOS SRAMs and Its Dependence on Well Engineering," IEEE Trans. Nuc. Sci. 54, pp. 2468-2473, 2007.
7. N. Seifert, et al., "Radiation-Induced Soft Error Rates of Advanced CMOS Bulk Devices," Intl Reliability Physics Symp. (IRPS), pp. 217-225, 2006.
8. A. D. Tipton, et al., "Multiple-Bit Upset in 130 nm CMOS Technology" IEEE Trans. Nuc. Sci., vol. 53, pp. 3259-3264, 2006.
9. J. Maiz, S. Hareland, K. Zhang and P. Armstrong, "Characterization of Multi-bit Soft Error Events in Advanced SRAMs," Intl Electron Devices Meeting (IEDM), pp. 21.4.1-21.4.1, 2003.
10. K. Osada, K. Yamaguchi, Y. Saitoh and T. Kawahara, "Cosmic-Ray Multi-Error Immunity for SRAM, Based on Analysis of the Parasitic Bipolar Effect," Symp. on VLSI Circuits Digest of Tech. Papers, pp. 255-258, 2003.
11. Y. Tosaka, H. Ehara, M. Igeta, T. Uemura, H. Oka, N. Matsuoka and K. Hatanaka, "Comprehensive Study of Soft Errors in Advanced CMOS Circuits with 90/130 nm Technology," Intl Electron Devices Meeting (IEDM), pp. 941-944, 2004.
12. E. Ibe, S. S. Chung, S. Wen, H. Yamaguchi, Y. Yahagi, H. Kameyama, S. Yamamoto and T. Akioka, "Spreading Diversity in Multi-cell Neutron-induced Upsets with Device Scaling," IEEE 2006 Custom Integrated Circuits Conf. (CICC), pp. 437-444, 2006.
13. H. Yamaguchi, E. Ibe, Y. Yahagi, S. Yamamoto, T. Akioka and H. Kameyama, "Novel Mechanisms of Neutron-Induced Multi-Cell Error in CMOS Devices Tracked down from 3D Device Simulation," 2006 Intl Conf. on Simulation of Semiconductor Processes and Devices, pp. 184-187, 2006.
14. C W. Slayman, "Cache and Memory Error Detection, Correction, and Reduction Techniques for Terrestrial Servers and Workstations," IEEE Trans. Dev. Mat. Rel., pp. 397-404, 2005.
15. E. H. Cannon, D. D. Reinhardt, M. S. Gordon and P. S. Makowenskyj, "SRAM SER in 90, 130 and 180 nm Bulk and SOI Technologies," Intl Reliability Physics Symp. (IRPS), pp. 300-304, 2004.
16. J. R. Schwank, V. Ferlet-Cavrois, M. R. Shaneyfelt, P. Paillet and P. E. Dodd, "Radiation Effects in SOI Technologies," IEEE Trans. Nuc. Sci., vol. 50, pp. 522-538, 2003, and references therein.
17. E. W. Caseio, J. M. Sisterson, J. B. Flanz and M. S. Wagner, "The Proton Irradiation Program at the Northeast Proton Therapy Center," IEEE Radiation Effects Data Workshop, pp. 141-144, 2003.
18. "JESD89-3 Test Method for Beam Accelerated Soft Error Rate," JEDEC Standards, 2004.
19. E. Leobandung, et al., "High Performance 65nm SOI Technology with Dual Stress Liner and Low Capacitance SRAM Cell," Symp. on VLSI Technology, pp. 126-127, 2002.
20. Z. Luo, et al., "High Performance and Low Power Transistors Integrated in 65nm Bulk CMOS Technology," Intl Electron Devices Meeting (IEDM), pp. 661-664, 2004.
21. A. KleinOsowski, P. Oldiges, R. Q. Williams and P. Solomon, "Modeling Single Event Upsets in 65nm Silicon-on-Insulator Semiconductor Devices" IEEE Trans. Nuc. Sci, vol. 53, pp. 3321-3328, 2006.
22. "JESD89-2 Test Method for Alpha Source Accelerated Soft Error Rate," JEDEC Standards, 2004.
23. H. H. K. Tang and E. H. Cannon, "SEMM2: A Modeling System for Single Event Upset Analysis," IEEE Trans. Nuc. Sci. 51, pp. 3342-3348, 2004, and references therein.
24. G. Gasiot, D. Giot and P. Roche, "Alpha-Induced Multiple Cell Upsets in Standard and Radiation Hardened SRAMs Manufactured in a 65nm CMOS Technology," IEEE Trans. Nuc. Sci., vol. 53, pp. 3479-3486, 2006.