Single-event transient pulse propagation in digital CMOS

IEEE Transactions on Nuclear Science

Volumn 55, Issue 6, 2008, Pages 2861-2871

  Massengill, Lloyd W ^a   Tuinenga, Paul W ^b  

^a VANDERBILT UNIVERSITY   (United States)

^b VANDERBILT UNIVERSITY   (United States)

Author keywords

Pulse broadening; Pulse propagation; Pulse stretching; Single event transients; Single events

Indexed keywords

DYNAMIC RESPONSE;

PULSE BROADENING; PULSE PROPAGATION; PULSE STRETCHING; SINGLE EVENT TRANSIENTS; SINGLE EVENTS;

TRANSIENTS;

EID: 58849135802     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2008.2006749     Document Type: Conference Paper

References (25)

1. M. P. Baze and S. P. Buchner, "Attenuation of single event induced pulses in CMOS combinational logic," IEEE Trans. Nucl. Sci., vol. 44, no. 6, pp. 2217-2223, Dec. 1997.
2. M. J. Gadlage, R. D. Schrimpf, J. M. Benedetto, P. H. Eaton, D. G. Mavis, M. Sibley, K. Avery, and T. L. Turflinger, "Single event transient pulsewidths in digital microcircuits," IEEE Trans. Nucl. Sci., vol. 51, no. 6, pp. 3285-3290, Dec. 2004.
3. D. G. Mavis and P. H. Eaton, "Soft error rate mitigation techniques for modern microcircuits," in Proc. Int. Reliability Physics Symp., Apr. 2002, pp. 216-225.
4. P. E. Dodd, M. R. Shaneyfelt, J. A. Felix, and J. R. Schwank, "Production and propagation of single-event transients in high-speed digital logic ICs," IEEE Trans. Nucl. Sci., vol. 51, no. 6, pp. 3278-3284, Dec. 2004.
5. V. Ferlet-Cavrois, P. Paillet, M. Gaillardin, D. Lambert, J. Baggio, J. R. Schwank, G. Vizkelethy, M. R. Shaneyfelt, K. Hirose, E. W. Blackmore, O. Faynot, C. Jahan, and L. Tosti, "Statistical analysis of the charge collected in SOI and bulk devices under heavy ion and proton irradiation - implications for digital SETs," IEEE Trans. Nucl. Sci., vol. 53, no. 6, pp. 3242-3252, Dec. 2006.
6. M. Gaillardin, P. Paillet, V. Ferlet-Cavrois, J. Baggio, D. McMorrow, O. Faynot, C. Jahan, L. Tosti, and S. Cristoloveanu, "Transient radiation response of single- and multiple-gate FD SOI transistors," IEEE Trans. Nucl. Sci., vol. 54, no. 6, pp. 2355-2362, Dec. 2007.
7. J. M. Benedetto, P. H. Eaton, D. G. Mavis, M. Gadlage, and T. Turflinger, "Variation of digital SET pulse widths and the implications for single event hardening of advanced CMOS proceses," IEEE Trans. Nucl. Sci., vol. 52, no. 6, pp. 2114-2119, Dec. 2005.
8. J. M. Benedetto, P. H. Eaton, D. G. Mavis, M. Gadlage, and T. Turflinger, "Digital single event transient trends with technology node scaling," IEEE Trans. Nucl. Sci., vol. 53, no. 6, pp. 3462-3465, Dec. 2006.
9. M. P. Baze, J. Wert, J. W. Clement, M. G. Hubert, A. Witulski, O. A. Amusan, L. W. Massengill, and D. McMorrow, "Propagating SET characterization techniques for digital CMOS libraries," IEEE Trans. Nucl. Sci., vol. 53, no. 6, pp. 3472-3478, Dec. 2006.
10. V. Ferlet-Cavrois, P. Paillet, D. McMorrow, N. Fel, J. Baggio, S. Girard, O. Duhamel, J. S. Melinger, M. Gaillardin, J. R. Schwank, P. E. Dodd, M. R. Shaneyfelt, and J. A. Felix, "New insights into single event transient propagation in chains of inverters - evidence for propagation-induced pulse broadening," IEEE Trans. Nucl. Sci., vol. 54, no. 6, pp. 2338-2346, Dec. 2007.
11. J. R. Burns, "Switching response of complementary-symmetry MOS transistor logic circuits," RCA Rev., vol. XXV, no. 4, pp. 627-661, Dec. 1964.
12. D. Auvergne, J. M. Daga, and M. Rezzoug, "Signal transition time effect on CMOS delay evaluation," IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 47, no. 9, pp. 1362-1369, Sep. 2000.
13. J. P. Uyemura, CMOS Logic Circuit Design. Norwell, MA: Kluwer, 1999.
14. N. Hedenstierna and K. O. Jeppson, "CMOS circuit speed and buffer optimization," IEEE Trans. Comput.-Aided Des., vol. CAD-6, no. 3, pp. 270-281, Mar. 1987.
15. A. I. Kayssi, K. A. Sakallah, and T. M. Burks, "Analytical transient response of CMOS inverters," IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 39, no. 1, pp. 42-45, Jan. 1992.
16. M. J. Gadlage, R. D. Schrimpf, B. Narasimham, B. L. Bhuva, P. H. Eaton, and J. M. Benedetto, "Effect of voltage fluctuations on the single event transient response of deep submicron digital circuits," IEEE Trans. Nucl. Sci., vol. 54, no. 6, pp. 2495-2499, Dec. 2007.
17. D. Suh and J. G. Fossum, "Dynamic floating-body instabilities in partially depleted SOI CMOS circuits," in Proc. Int. Electron Devices Meeting, Dec. 1994, pp. 116-664.
18. S. Krishnan and J. G. Fossum, "Grasping SOI floating-body effects," IEEE Circuits Dev., pp. 32-37, Jul. 1998.
19. R. A. Schiebel, T. W. Houston, R. Rajgopal, and K. Joyner, "A study of floating-body effects on inverter chain delay," in Proc. 1995 IEEE Int. SOI Conf., Oct. 1995, pp. 125-126.
20. A.Wei, D. A. Antoniadis, and L. A. Blair, "Minimizing floating-bodyinduced threshold voltage variation in partially depleted SOI CMOS," IEEE Electron Device Lett., vol. 17, pp. 391-394, Aug. 1996.
21. T. W. Houston and S. Unnikrishnan, "A guide to simulation of hysteretic gate delays based on physical understanding," in Proc. 1998 Int. SOI Conf., Oct. 1998, pp. 121-122.
22. T. Ernst, F. Allibert, C. Perret, and S. Cristoloveanu, "Average transient current in SOI MOSFEs: A new technique for measuring the transient floating body effects," in Proc 2000 IEEE Int. SOI Conf., Oct. 2000, pp. 64-65.
23. A. Wei, M. J. Sherony, and D. A. Antoniadis, "Effect of floating-body charge on SOI MOSFET design," IEEE Trans. Electron Devices, vol. 45, no. 2, pp. 430-438, Feb. 1998.
24. D. McMorrow, V. Ferlet-Cavrois, P. Paillet, and J. Baggio, "Singleevent transient propagation in combinational logic," presented at the 2008 SEE Symp., Long Beach, CA, Apr. 2008.
25. V. Pouget, A. Douin, D. Lewis, and P. Fouillat, "Characterization of single-event transient broadening in 130 nm inverter chains," presented at the 2008 SEE Symp., Long Beach, CA, Apr. 2008.