Investigation of soft error rate including multi-bit upsets in advanced SRAM using neutron irradiation test and 3D mixed-mode device simulation

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2004, Pages 945-948

  Kawakami, Yukiya ^a   Hane, Masami ^a   Nakamura, Hideyuki ^b   Yamada, Takashi ^b   Kumagai, Kouichi ^b  

^a NEC CORPORATION   (Japan)

^b RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

LATCH CIRCUITS; MIXED-MODE DEVICE SIMULATION; MULTI-BIT ERROR; SOFT ERROR RATE (SER);

BIT ERROR RATE; COMPUTATIONAL METHODS; COMPUTER SIMULATION; MATHEMATICAL MODELS; NEUTRON IRRADIATION; OPTIMIZATION;

STATIC RANDOM ACCESS STORAGE;

EID: 21644469547     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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