Impact of scaling on neutron-induced soft error in SRAMs from a 250 nm to a 22 nm design rule

IEEE Transactions on Electron Devices

Volumn 57, Issue 7, 2010, Pages 1527-1538

  Ibe, Eishi ^a   Taniguchi, Hitoshi ^a   Yahagi, Yasuo ^a   Shimbo, Ken Ichi ^a   Toba, Tadanobu ^a  

^a HITACHI LTD   (Japan)

Author keywords

Bit multiplicity; cosmic ray impact simulator (CORIMS); multi cell upset (MCU); multi node upset (MNU); scaling; single event upset (SEU); static random access memories (SRAMs)

Indexed keywords

DESIGN RULES; ERROR DATA; FIELD TEST; HIGH ALTITUDE; LOW-ENERGY NEUTRONS; MONTE CARLO SIMULATORS; MULTICELL; NEUTRON FIELDS; NUCLEAR REACTIONS; SINGLE EVENT UPSET (SEU); SINGLE EVENT UPSETS; SOFT ERROR; SOFT ERROR RATE; STATIC RANDOM ACCESS MEMORY;

BIT ERROR RATE; COSMIC RAYS; COSMOLOGY; FLIP FLOP CIRCUITS; NEUTRONS; NUCLEAR REACTORS; REACTION RATES; SIMULATORS;

STATIC RANDOM ACCESS STORAGE;

EID: 77954030094     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2010.2047907     Document Type: Article

References (57)

1. N. Sugii, R. Tsuchiya, T. Ishigaki, Y. Morita, H. Yoshimoto, K. Torii, and S. Kimura, "Comprehensive study on Vth variability in silicon on thin BOX (SOTB) CMOS with small random-dopant fluctuation: Finding a way to further reduce variation," in IEDM Tech. Dig., San Francisco, CA, Dec. 15-17, 2008, pp. 249-253.
2. S. Wen, R. Wong, and A. Silburt, "IC Component SEU impact analysis," in Proc. SELSE4, Mar. 26-27, 2008, pp. 37-40.
3. D. Villanueva, A. Pouydebasque, E. Robilliart, T. Skotnicki, E. Fuchs, and H. Jaoue, "Impact of the lateral source/drain abruptness on MOSFET characteristics and transport properties," in IEDM Tech. Dig.,Washington, DC, Dec. 7-10, 2003, pp. 9.4.1-9.4.4.
4. L. T. Clark, K. C. Moh, K. E. Holbert, X. Yao, J. Knudsen, and H. Shah, "Optimizing radiation hard by design SRAM cells," IEEE Trans. Nucl. Sci., vol.54, no.6, pp. 2028-2036, Dec. 2007.
5. E. Ibe, S. Chung, S. Wen, Y. Yahagi, H. Kameyama, and Yamamoto, "Multi-error propagation mechanisms clarified in CMOSFET SRAM devices under quasi-mono energetic neutron irradiation," in Proc. NSREC, Ponte Vedra Beach, FL, Jul. 17-21, 2006, No.PC-6.
6. E. Ibe, S. Chung, S. Wen, Y. Yahagi, H. Kameyama, S. Yamamoto, T. Akioka, and H. Yamaguchi, "Valid and prompt track-down algorithms for multiple error mechanisms in neutron-induced single event effects of memory devices," in Proc. RADECS, Athens, Greece, Sep. 27-29, 2006, No.D-2.
7. D. Radaelli, H. Puchner, P. Chia, S.Wong, and S. Daniel, "Investigation of multi-bit upsets in a 150 nm technology SRAM device," in Proc. NSREC, Seattle, WA, Jul. 11-15, 2005, No.F-4.
8. N. Seifert and V. Zia, "Assessing the impact of scaling on the efficacy of spatial redundancy based mitigation schemes for terrestrial applications," in Proc. IEEE SELSE3, Austin, TX, Apr. 3-4, 2007.
9. E. Ibe, S. Chung, H. Yamaguchi, Y. Yahagi, H. Kameyama, S. Yamamoto, and T. Akioka, "Spreading diversity in multi-cell neutron-induced upsets with device scaling," in Proc. CICC, San Jose, CA, Sep. 10-13, 2006, pp. 437-444.
10. K. Pagiamtzis, N. Azizi, and F. Najm, "A soft-error tolerant contentaddressable memory (CAM) using an error-correcting-match scheme," in Proc. CICC, 2006, pp. 301-304.
11. A. Wood, R. Jardine, and W. Bartlett, "Data integrity in HP nonstop servers," in Proc. SELSE II, Urbana-Champain, IL, Apr. 11-12, 2006.
12. D. Skarin and J. Karlsson, "Software mechanisms for tolerating soft errors in an automotive brake-controller," in Proc. WDSN, Lisbon, Portugal, Jun. 29, 2009, pp. D34-D38.
13. P. C. Monferrer, X. Vera, J. C. Casado, and J. Abella, "Soft-error protection mechanisms for in-order cores," in Proc. SELSE4, Mar. 26-27, 2008, pp. 20-25.
14. L. R. Rockett, "An SEU-hardened CMOS latch design," IEEE Trans. Nucl. Sci., vol.35, no.6, pp. 1682-1687, Dec. 1988.
15. M. Li, M. Pradeep, R. S. Sahoo, S. Adve, V. Adve, and Y. Y. Zhou, "SWAT: An error resilient system," in Proc. SELSE4, Mar. 26-27, 2008, pp. 8-13.
16. R. Velazco, D. Bessot, S. Duzellier, R. Ecoffet, and R. Koga, "Two CMOS memory cells suitable for the design of SEU-tolerant VLSI circuits," IEEE Trans. Nucl. Sci., vol.41, no.6, pp. 2229-2234, Dec. 1994.
17. T. Uemura, R. Tanabe, Y. Tosaka, and S. Satoh, "Mitigation techniques using low pass filters against single event transients in 45 nm-technology LSIs," in Proc. IOLTS, Rhodes, Greece, Jul.7-9, 2008, pp. 117-122, No.iolts08-15.
18. K. J. Hass, J. W. Gambles, B. Walker, and M. Zampagione, "Mitigating single event upsets from combinational logic," in Proc. 7th NASA Symp. VLSI Des., 1998, pp. 4.1.1-4.1.10.
19. T. Calin, M. Nicolaidis, and R. Velazco, "Upset hardened memory design for submicron CMOS technology," IEEE Trans. Nucl. Sci., vol.43, no.6, pp. 2874-2878, Dec. 1996.
20. A. Lesea and K. Castellani-Coulie, "Experimental study and analysis of soft errors in 90 nm Xilinx FPGA and beyond," in Proc. RADECS, Deauville, France, Sep.10-14, 2007, pp. 1-5, No.DWL-16.
21. S. Rezgui, J.-J. Wang, E. C. Tung, B. Cronquist, and J. McCollum, "New methodologies for SET characterization and mitigation in flash-based FPGAs," in Proc. NSREC, Honolulu, HI, Jul. 23-27, 2007, No.J-8.
22. Functional Safety of Electrical/Electronic/Programmable Electronic Safety-Related Systems, IEC61508, 1998.
23. N. Seifert, "Soft error rates of hardened sequentials utilizing local redundancy," in Proc. IOLTS, Rhodes, Greece, Jul. 6-9, 2008, pp. 49-52, No. S1.3.
24. O. A. Amusan, L. W. Massengill, B. L. Bhuva, P. R. Fleming, and M. L. Alles, "Charge collection and sharing in a 130 nm CMOS technology," in Proc. NSREC, Ponte Vedra Beach, FL, Jul. 17-21, 2006, No.C-3.
25. B. D. Olson, D. Ball, K. M. Warren, L. W. Massengill, N. F. Haddad, S. E. McMorrow, and D. Doyle, "Simultaneous single event charge sharing and parasitic bipolar conduction in a highly-scaled SRAM design," IEEE Trans. Nucl. Sci., vol.52, no.6, pp. 2132-2136, Dec. 2005.
26. T. Nakamura, E. Ibe, M. Baba, Y. Yahagi, and H. Kameyama, Terrestrial Neutron-Induced Soft-Error in Advanced Memory Devices. Singapore: World Scientific, 2008.
27. H. H. K. Tang, G. R. Srinivasan, and N. Azziz, "Cascade statistical model for nucleon-induced reactions on light nuclei in the energy range 50-MeV-1 GeV," Phys. Rev. C, Nucl. Phys., vol.42, no.4, pp. 1598-1622, Oct. 1990.
28. I. Dostrovsky, Z. Fraenkel, and G. Friedlander, "Monte Carlo calculations of nuclear evaporation process. III. Applications to low-energy reactions," Phys. Rev., vol.116, no.3, pp. 683-702, Nov. 1959.
29. C. Hu, "Alpha-particle-induced field and enhanced collection of carriers," IEEE Electron Device Lett., vol.EDL-3, no.2, pp. 31-34, Feb. 1982.
30. S. Furihata, "Parameters used in GEM," Ph.D. dissertation, Tohoku Univ., Sendai, Japan, 2002.
31. F. Bertland and R. Peele, "Complete hydrogen and helium particle spectra from 30- to 60-MeV proton bombardment of nuclei with A = 12 to 209 and comparison with the intranuclear cascade model," Phys. Rev. C, Nucl. Phys., vol.8, no.3, pp. 1045-1064, Sep. 1973.
32. JEDEC, "Measurement and Reporting of Alpha Particles and Terrestrial Cosmic Ray-Induced Soft Errors in Semiconductor Devices: JESD89A," JEDEC STANDARD, JEDEC Solid State Technology Association, pp. 1-85, 2006, No.89.
33. E. J. Montes, A. Reed, J. A. Pellish, M. L. Alles, R. D. Schrimpf, R. Vizkelethy, M. Varadharajaperumal, G. Niu, A. K. Sutton, Diestelhorst, G. Espinel, R. Krithivasan, J. P. Comeau, J. D. Cressler, and P. W. Marshall, "Single event upset mechanisms for low energy deposition events in SiGe HBTs," in Proc. NSREC, Ponte Vedra Beach, FL, Jul. 17-21, 2006, No.C-9.
34. [Online]. Available: http://www.buchanan1.net/stream-description.shtml
35. E. L. Petersen, J. C. Pickel, E. C. Smith, P. J. Rudeck, and J. R. Letaw, "Geometrical factors in SEE rate calculation," IEEE Trans. Nuclear Sci., vol.40, no.6, pp. 1888-1909, Dec. 1993.
36. [Online]. Available: http://www.srim.org/
37. [Online]. Available: http://http://www.itrs.net/Links/2007ITRS/ Home2007.htm
38. E. Ibe, Y. Yahagi, H. Kameyama, and Y. Takahashi, "Single event effects of semiconductor devices at the ground," Ionizing Radiation, vol.30, no.7, pp. 263-281, 2004.
39. P. W. Lisowski, "The Los Alamos National Laboratory spallation neutron sources," Nucl. Sci. Eng., vol.106, pp. 208-218, 1990.
40. A. V. Prokofiev, O. Bystrom, C. Ekstrom, V. Ziemann, J. Blomgren, S. Pomp, M. Osterlund, and U. Tippawan, "The TSL neutron beam facility," in Proc. 10th Symp. Neutron Dosimetry, Uppsala, Sweden, Jun. 12-16, 2006.
41. M. Baba, H. Okamura, M. Hagiwara, T. Itoga, S. Kamada, Y. Yahagi, and E. Ibe, "Installation and application of an intense 7Li (p, n) neutron source for 20-90 MeV region," Radiat. Prot. Dosim., vol.126, no.1-4, pp. 13-17, 2007.
42. M. Baba, M. Takada, T. Iwasaki, S. Matsuyama, T. Nakamura, H. Ohguchi, T. Nakao, T. Sanami, and N. Hirakawa, "Development of monoenergetic neutron calibration fields between 8 keV and 15 MeV," Nucl. Instrum. Methods Phys. Res. A, Accel. Spectrom. Detect. Assoc. Equip., vol.376, no.1, pp. 115-123, Jun. 1996.
43. E. Ibe, "Current and future trend on cosmic-ray-neutron induced single event upset at the ground down to 0.1-micron-device," in Proc. Svedberg Lab. Workshop Appl. Phys., Uppsala, Sweden, May 3, 2001, No.1.
44. A. Dixit, R. Heald, and A. Wood, "Trends from ten years of soft error experimentation," in Proc. SELSE 5, Mar. 24-25, 2009.
45. E. Ibe, H. Kameyama, Y. Yahagi, K. Nishimoto, and Y. Takahashi, "Distinctive asymmetry in neutron-induced multiple error patterns of 0.13 umocess SRAM," in Proc. 6th Int. Workshop Radiation Effects Semiconductor Devices Space Appl., Tsukuba, Japan, Oct. 6-8, 2004, pp. 19-23.
46. R. K. Lawrence, J. F. Ross, N. Haddad, D. Albrect, R. A. Reed, and M. A. McMahan-Norris, "Soft error sensitivities in 90 nm Bulk CMOS SRAMs," in Proc. NSREC, Quebec, QC, Canada, Jul. 20-24, 2009, No.W-4.
47. B. D. Sierawski, J. A. Pellish, R. A. Reed, R. D. Schrimpf, K. M. Warren, R. A. Weller, M. H. Mendenhal, A. D. Tipton, M. A. Xapsos, R. C. Baumann, X. Deng, M. J. Campola, M. R. Friendlich, H. S. Kim, A. M. Phan, and C. M. Seidleck, "Impact of low-energy proton induced upsets on test methods and rate predictions," IEEE Trans. Nucl. Sci., vol.56, no.6, pp. 3085-3092, Dec. 2009.
48. D. F. Heidel, P. W. Marshall, J. A. Pellish, K. P. Rodbell, K. A. LaBe, J. R. Schwank, S. E. Rauch, M. C. Hakey, M. D. Berg, C. M. Castaneda, P. E. Dodd, M. R. Friendlich, A. D. Phan, C. M. Seidleck, M. R. Shaneyfelt, and M. A. Xapsos, "Single-event upsets and multiple-bit upsets on a 45 nm SOI SRAM," IEEE Trans. Nucl. Sci., vol.56, no.6, pp. 3499-3504, Dec. 2009.
49. T. D. Loveless, L. W. Massengil, B. L. Bhuva,W. T. Holman, R. A. Reed, D. McMorrow, J. S. Melinger, and P. Jenkins, "A single-event-hardened phase-locked loop fabricated in 130 nm CMOS," in IEEE Trans. Nucl. Sci., Dec. 2007, vol. 54, no. 6, pp. 2012-2020.
50. M. Cabanas-Holmen, E. Cannon, A. Kleinosowski, J. Killens, J. Ballast, and J. Socha, "Clock and reset transients in a 90 nm RHBD single-core tilera processor," in Proc. NSREC, Quebec, QC, Canada, Jul. 20-24, 2009, No.PG-3.
51. L. Borucki, G. Schindlbeck, and C. Slayman, "Comparison of accelerated DRAM soft error rates measured at component and system level," in Proc. IRPS, Phoenix, AZ, Apr. 27-May, 1, 2008, pp. 482-487, No. 5A.4.
52. A. V. Prokofiev, J. Blomgren, M. Majerle, R. Nolte, S. Rottger, S. P. Platt, C. X. Xiao, and A. N. Smirnov, "Characterization of the ANITA neutron Source for Accelerated SEE Testing at The Svedberg Laboratory," in Proc. IEEE Radiation Effects Data Workshop, Quebec City, QC, Canada, Jul. 20-24, 2009, pp. 166-173.
53. D. G. Mavis, P. H. Eaton, and M. D. Sibley, "SEE characterization and mitigation in ultra-deep submicron technologies," in Proc. ICICDT, Austin, TX, May 18-20, 2009, pp. 105-112.
54. A. V. Prokofiev, J. Blomgren, M. Majerle, R. Nolte, S. Rottger, S. P. Platt, and A. N. Smirnov, "Characterization of the ANITA neutron source for accelerated SEE testing at the Svedberg laboratory," in Proc. NSREC, Quebec, QC, Canada, Jul. 20-24, 2009, No.W-25.
55. E. W. Blackmore, "Development of a large area neutron beam for system testing at TRIUMF," in Proc. IEEE Radiation Effects Data Workshop, Quebec, QC, Canada, Jul. 20-24, 2009, pp. 157-160.
56. E. H. Cannon and M. Cabanas-Holmen, "Heavy ion and high energy proton-induced single event transients in 90 nm inverter, NAND and NOR gates," IEEE Trans. Nucl. Sci., vol.56, no.6, pp. 3511-3518, Dec. 2009.
57. T. Makino, D. Kobayashi, K. Hirose, D. Takahashi, S. Ishii, M. Kusano, S. Onoda, T. Hirao, and T. Ohshima, "Soft-error rate in a logic LSI estimated from SET pulse-width measurements," IEEE Trans. Nucl. Sci., vol.56, no.6, pp. 3180-3184, Dec. 2009.