Robust system design with built-in soft-error resilience

Computer

Volumn 38, Issue 2, 2005, Pages 43-52

  Mitra, Subhasish ^a,b   Seifert, Norbert ^c   Zhang, Ming ^a,d   Shi, Quan ^a   Kim, Kee Sup ^a  

^a INTEL CORPORATION   (United States)

^b Stanford University   (United States)

^c VIENNA UNIVERSITY OF TECHNOLOGY   (Austria)

^d UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMBINATORIAL CIRCUITS; DATA STORAGE EQUIPMENT; DESIGN FOR TESTABILITY; ERROR CORRECTION; FLIP FLOP CIRCUITS; LOGIC CIRCUITS; LOGIC DESIGN; SEQUENTIAL CIRCUITS; SILICON ON INSULATOR TECHNOLOGY;

CIRCUIT DESIGN; PARITY CODES; SOFT ERROR RATE;

MICROPROCESSOR CHIPS;

EID: 15044363155     PISSN: 00189162     EISSN: None     Source Type: Trade Journal    
DOI: 10.1109/MC.2005.70     Document Type: Article

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