A model for transient fault propagation in combinatorial logic

Proceedings - 9th IEEE International On-Line Testing Symposium, IOLTS 2003

Volumn , Issue , 2003, Pages 111-115

  Omana M ^a   Papasso, G ^a   Rossi, D ^a   Metra, C ^a  

^a UNIVERSITY OF BOLOGNA   (Italy)

Author keywords

Aerospace electronics; Charge carrier processes; Circuit faults; Circuit simulation; Combinational circuits; Logic devices; Mathematical model; Microelectronics; Silicon; Voltage

Indexed keywords

CIRCUIT SIMULATION; COMBINATORIAL CIRCUITS; ELECTRIC POTENTIAL; FAULT TREE ANALYSIS; INTEGRATED CIRCUITS; LOGIC DEVICES; MATHEMATICAL MODELS; MICROELECTRONICS; SILICON; SPICE;

AEROSPACE ELECTRONICS; CHARGE CARRIER PROCESS; CIRCUIT FAULTS; COMBINATORIAL LOGIC; HIGH RELIABILITY; HSPICE SIMULATIONS; MICRO-ELECTRONIC DEVICES; TRANSIENT FAULTS;

LOGIC CIRCUITS;

EID: 84944062057     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/OLT.2003.1214376     Document Type: Conference Paper

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