Measurements and analysis of SER-tolerant latch in a 90-nm dual-V T CMOS process

IEEE Journal of Solid-State Circuits

Volumn 39, Issue 9, 2004, Pages 1536-1543

  Hazucha, Peter ^a   Karnik, Tanay ^a   Walstra, Steven ^a   Bloechel, Bradley A ^a   Tschanz, James W ^a   Maiz, Jose ^a   Soumyanath, Krishnamurthy ^a   Dermer, Gregory E ^a   Narendra, Siva ^a   De, Vivek ^a   Borkar, Shekhar ^a  

^a INTEL CORPORATION   (United States)

Author keywords

Error control coding; Radiation hardened latch; Reliability; Single event upset; Soft error rate; Soft errors

Indexed keywords

ERROR CONTROL CODING; RADIATION HARDENED LATCH; SINGLE EVENT UPSETS (SEU); SOFT ERROR RATES (SER); SOFT ERRORS;

ERROR ANALYSIS; MICROPROCESSOR CHIPS; NEUTRON BEAMS; RADIATION HARDENING; REDUNDANCY; RELIABILITY; THRESHOLD VOLTAGE; TRANSISTORS;

CMOS INTEGRATED CIRCUITS;

EID: 4444365711     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2004.831449     Document Type: Conference Paper

References (13)

1. J. F. Ziegler, 'Terrestrial cosmic rays," in IBM J. Res. Develop., vol. 40, Jan. 1996, pp. 19-39.
2. R. C. Baumann, "Soft errors in advanced semiconductor devices-part I: The three radiation sources," IEEE Trans. Device Mat. Reliabil., vol. 1, pp. 17-22, Mar. 2001.
3. Y. Tosaka et al., "Measurement and analysis of neutron-induced soft errors in sub-half-micron CMOS circuits." IEEE Trans. Electron. Devices, vol. 45, pp. 1453-1458, July 1998.
4. P. Hazucha and C. Svensson, "Impact of CMOS technology scaling on the atmospheric neutron soft error rate," IEEE Trans. Nucl. Sci., vol. 47, pp. 2586-2594, Dec. 2000.
5. T. Karnik, B. Bloechel, K. Soumyanath, V. De, and S. Borkar, "Scaling trends of cosmic ray induced soft errors in static latches beyond 0.18 μm," in IEEE Symp. VLSI Circuits, June 2001, pp. 61-62.
6. P. Hazucha et al., "Neutron soft error rate measurements in a 90-nm CMOS process and scaling trends in SRAM from 0.25 μm to 90-nm generation," in IEEE IEDM Tech. Dig., Dec. 2003, pp. 523-526.
7. G. Hammond and S. Naffziger, "Next generation Itanium processor overview," Intel Developer Forum, pp. 27-30, Aug. 2001.
8. K. J. Hass, R. K. Treece, and A. E. Giddings, "A radiation-hardened 16/32-bit microprocessor," IEEE Trans. Nucl. Sci., vol. 36, pp. 2252-2257, Dec. 1989.
9. T. Karnik, S. Vangal, V. Veeramachaneni, P. Hazucha, V. Erraguntla, and S. Borkar, "Selective node engineering for chip-level soft error rate improvement," IEEE Symp. VLSI Circuits, pp. 204-205, June 2002.
10. T. Calin, M. Nicolaidis, and R. Velazco, "Upset hardened memory design for submicron CMOS technology," IEEE Trans. Nucl. Sci., vol. 43, pp. 2874-2878, Dec. 1996.
11. S. Thompson et al., "A 90 nm logic technology featuring 50 nm strained silicon channel transistors, 7 layers of Cu interconnects, low k ILD, and 1 μm 2 SRAM cell," IEEE IEDM Tech. Dig., pp. 61-64, Dec. 2002.
12. JEDEC Standard JESD89, 2001.
13. J. Maiz, S. Hareland, K. Zhang, and P. Armstrong, "Characterization of multi-bit soft error event in advanced SRAMs," in IEEE IEDM Tech. Dig., Dec. 2003, pp. 519-522.