Comprehensive study of soft errors in advanced CMOS circuits with 90/130 nm technology

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2004, Pages 941-944

  Tosaka, Y ^a   Ehara, H ^a   Igeta, M ^a   Uemura, T ^a   Oka, H ^a   Matsuoka, N ^b   Hatanaka, K ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

^b OSAKA UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRON BEAMS; ERROR CORRECTION; ERRORS; FLIP FLOP CIRCUITS; INTEGRATED CIRCUIT LAYOUT; LOGIC CIRCUITS; NEUTRON SCATTERING; STATIC RANDOM ACCESS STORAGE; CMOS INTEGRATED CIRCUITS; TIMING CIRCUITS;

LATCH CIRCUITS; MULTIPLEBIT; SOFT ERRORS; WHITE BEAMS;

CMOS INTEGRATED CIRCUITS; RADIATION HARDENING;

ACCELERATED TESTS; ADVANCED CMOS; CMOS-CIRCUITS; HIGH-ENERGY NEUTRON; LATCH CIRCUITS; MULTIPLE BITS; PROCESS DEPENDENCE; SOFT ERROR;

EID: 21644463896     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

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