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Volumn I, Issue , 2005, Pages 282-287

Accurate reliability evaluation and enhancement via probabilistic transfer matrices

Author keywords

[No Author keywords available]

Indexed keywords

ALGEBRAIC DECISION DIAGRAMS (ADD); FAULT TOLERANT DESIGN; PROBABILISTIC TRANSFER MATRICES (PTM); SOFT ERRORS;

EID: 33646902164     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2005.47     Document Type: Conference Paper
Times cited : (260)

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    • Evaluating circuit reliability under probabilistic gate-level fault models
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    • K.N. Patel, J.P. Hayes, and I.L. Markov, "Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault Models," IWLS, May 2003, pp. 59-64.
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    • Patel, K.N.1    Hayes, J.P.2    Markov, I.L.3
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.