-
2
-
-
0346148456
-
A probabilistic based design methodology for nanoscale computation
-
R.I. Bahar, J. Mundy and J. Chan, "A Probabilistic Based Design Methodology for Nanoscale Computation", ICCAD, 2003, pp. 480-486.
-
(2003)
ICCAD
, pp. 480-486
-
-
Bahar, R.I.1
Mundy, J.2
Chan, J.3
-
3
-
-
0031122218
-
Algebraic decision diagrams and their applications
-
April-May
-
R.I. Bahar et al., "Algebraic Decision Diagrams and their Applications," J. of Formal Methods in Sys. Design 10, no.2/3, April-May 1997, pp. 171-206.
-
(1997)
J. of Formal Methods in Sys. Design
, vol.10
, Issue.2-3
, pp. 171-206
-
-
Bahar, R.I.1
-
4
-
-
0002538699
-
Multi-terminal binary decision diagrams and hybrid decision diagrams
-
T. Sasao and M. Fujita, eds, Kluwer
-
E. Clarke et al., "Multi-Terminal Binary Decision Diagrams and Hybrid Decision Diagrams," in T. Sasao and M. Fujita, eds, Representations of Discrete Functions, Kluwer, 1996, pp. 93-108.
-
(1996)
Representations of Discrete Functions
, pp. 93-108
-
-
Clarke, E.1
-
6
-
-
0012223405
-
A system architecture solution for unreliable nanoelectronic devices
-
December
-
J. Han, P. Jonker, "A System Architecture Solution for Unreliable Nanoelectronic Devices,"IEEE Trans. on Nanotechnology, vol. 1, December 2002 pp. 201-208.
-
(2002)
IEEE Trans. on Nanotechnology
, vol.1
, pp. 201-208
-
-
Han, J.1
Jonker, P.2
-
7
-
-
33646950897
-
Probability analysis of combination systems and their reliability
-
Nov-Dec.
-
V. L. Levin,"Probability Analysis of Combination Systems and their Reliability,"Engin. Cybernetics, no 6. Nov-Dec. 1964, pp. 78-84.
-
(1964)
Engin. Cybernetics
, Issue.6
, pp. 78-84
-
-
Levin, V.L.1
-
8
-
-
0142184763
-
Cost-effective approach for reducing soft error failure rate in logic circuits
-
K. Mohanram and N. A. Touba, "Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits," ITC, 2003, pp. 893-901.
-
(2003)
ITC
, pp. 893-901
-
-
Mohanram, K.1
Touba, N.A.2
-
9
-
-
33744479056
-
Evaluating circuit reliability under probabilistic gate-level fault models
-
May
-
K.N. Patel, J.P. Hayes, and I.L. Markov, "Evaluating Circuit Reliability Under Probabilistic Gate-Level Fault Models," IWLS, May 2003, pp. 59-64.
-
(2003)
IWLS
, pp. 59-64
-
-
Patel, K.N.1
Hayes, J.P.2
Markov, I.L.3
-
10
-
-
0036931372
-
Modeling the effect of technology trends on soft error rate of combinational logic
-
P. Shivakumar, M. Kistler, et. al, "Modeling the Effect of Technology Trends on Soft Error Rate of Combinational Logic" Intl. Conf. on Dependable Systems and Networks, 2002, pp. 389-398.
-
(2002)
Intl. Conf. on Dependable Systems and Networks
, pp. 389-398
-
-
Shivakumar, P.1
Kistler, M.2
-
11
-
-
0027277241
-
An efficient partitioning strategy for pseudo-exhaustive testing
-
R. Srinivasan, S.K. Gupta and M. A. Breuer, "An Efficient Partitioning Strategy for Pseudo-Exhaustive Testing" DAC, 1993, pp. 242-248.
-
(1993)
DAC
, pp. 242-248
-
-
Srinivasan, R.1
Gupta, S.K.2
Breuer, M.A.3
-
12
-
-
11344251915
-
Improving gate-level simulation of quantum circuits
-
October
-
G. F. Viamontes, I. L. Markov and J. P. Haves, "Improving Gate-Level Simulation of Quantum Circuits", Quantum Information Processing, vol. 2(5), October 2003, pp. 347-380. http://arxiv.org/abs/quant-ph/0309060
-
(2003)
Quantum Information Processing
, vol.2
, Issue.5
, pp. 347-380
-
-
Viamontes, G.F.1
Markov, I.L.2
Haves, J.P.3
-
13
-
-
0003133883
-
Probabilistic logics & synthesis of reliable organisms from unreliable components
-
J. von Neumann,"Probabilistic Logics & Synthesis of Reliable Organisms from Unreliable Components," Automata Studies, 56, pp. 43-98.
-
Automata Studies
, vol.56
, pp. 43-98
-
-
Von Neumann, J.1
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