Soft error rate analysis for combinational logic using an accurate electrical masking model

Proceedings of the IEEE International Conference on VLSI Design

Volumn , Issue , 2007, Pages 165-170

  Wang, Feng ^a   Xie, Yuan ^a   Rajaraman, R ^a   Vaidyanathan, B ^a  

^a PENNSYLVANIA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER PROGRAMMING LANGUAGES; ELECTRIC NETWORK ANALYSIS; EMBEDDED SYSTEMS; INTEGRATED CIRCUITS; MODAL ANALYSIS; MOSFET DEVICES; PULSE GENERATORS; SWITCHING CIRCUITS; SWITCHING THEORY; TABLE LOOKUP; TRANSISTOR TRANSISTOR LOGIC CIRCUITS;

COMBINATIONAL LOGIC CIRCUITS; COMBINATIONAL LOGICS; HSPICE SIMULATIONS; MASKING MODELS; MODEL MATCHES; MOS TRANSISTORS; MOSFET MODELS; NONLINEAR PROPERTIES; PROPAGATION MODELS; PULSE GENERATIONS; PULSE PROPAGATION MODELS; SOFT ERROR RATES; SUB MICRONS; TRANSIENT PULSES;

LOGIC CIRCUITS;

EID: 48349129464     PISSN: 10639667     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VLSID.2007.145     Document Type: Conference Paper

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