SEU and set modeling and mitigation in deep submicron technologies

Annual Proceedings - Reliability Physics (Symposium)

Volumn , Issue , 2007, Pages 293-305

  Mavis, David G ^a   Eaton, Paul H ^a  

^a Microelectronics Research and Development Corporation   (United States)

Author keywords

DSET; Radiation hardening; SER; SEU; Soft error; Transient; Upset

Indexed keywords

CIRCUIT SIMULATION; CMOS INTEGRATED CIRCUITS; HEAVY IONS; INTEGRATED CIRCUIT LAYOUT; RADIATION HARDENING; TRANSIENT ANALYSIS;

DIGITAL SINGLE EVENT TRANSIENT (DSET); MICROCIRCUITS; SINGLE EVENT UPSET (SEU); SOFT ERRORS;

MICROELECTRONICS;

EID: 34548705997     PISSN: 00999512     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/RELPHY.2007.369907     Document Type: Conference Paper

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