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Volumn 53, Issue 6, 2006, Pages 3466-3471

Digital device error rate trends in advanced CMOS technologies

Author keywords

Heavy ion; Ion radiation effects; Single event upset (SEU)

Indexed keywords

BIT ERROR RATE; DIGITAL CIRCUITS; HEAVY IONS; RADIATION EFFECTS;

EID: 33846280815     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2006.886212     Document Type: Conference Paper
Times cited : (29)

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    • M. P. Baze and S. P. Buchner, "Attenuation of single event induced pulses in CMOS combinatorial logic," IEEE Trans. Nucl. Sci., vol. 44, pp. 2217-2223, Dec. 1997.
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    • J. Benedetto, P. Eaton, K. Avery, D. Mavis, M. Gadlage, and T. Turflinger, "Variations of digital SET pulse widths and the implications for single event hardening of advanced CMOS processes," IEEE Trans. Nucl. Sci., vol. 52, pp. 2114-2119, Dec. 2005.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.