Cost-Effective Approach for Reducing Soft Error Failure Rate in Logic Circuits

IEEE International Test Conference (TC)

Volumn , Issue , 2003, Pages 893-901

  Mohanram, Kartik ^a,b   Touba, Nur A ^a  

^a The University of Texas at Austin   (United States)

^b Rice University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ERROR ANALYSIS; HEURISTIC METHODS; SEMICONDUCTOR MATERIALS;

CONCURRENT ERROR DETECTION (CED);

LOGIC CIRCUITS;

EID: 0142184763     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (33)

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