Characterization of Multi-bit Soft Error events in advanced SRAMs

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2003, Pages 519-522

  Maiz, Jose ^a   Hareland, Scott ^a   Zhang, Kevin ^a   Armstrong, Patrick ^a  

^a INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ERROR CORRECTION CODES (ECC); SINGLE EVENT UPSETS (SEU);

CACHE MEMORY; CMOS INTEGRATED CIRCUITS; CODES (SYMBOLS); DATA REDUCTION; ELECTRIC POTENTIAL; ERROR ANALYSIS; ERROR CORRECTION; LOGIC GATES; NEUTRON BEAMS; PROBABILITY; SILICON WAFERS; STATISTICAL METHODS; SUBSTRATES;

STATIC RANDOM ACCESS STORAGE;

EID: 0842266592     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. R. Baumann, 2002 Int. Rel. Phys. Symp tutorial on Soft Errors
2. J. Ziegler et al, IBM Journal of R&D, 1996
3. M. Bohr et al, 2000 IEEE Int. Elect. Dev. Conf.
4. S. Thompson et al. 2002 IEEE Int. Elect. Dev. Conf.