Multiple cell upsets as the key contribution to the total ser of 65 nm CMOS SRAMs and its dependence on well engineering

IEEE Transactions on Nuclear Science

Volumn 54, Issue 6, 2007, Pages 2468-2473

  Gasiot, G ^a   Giot, D ^a   Roche, P ^a  

^a STMICROELECTRONICS   (France)

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFICATION; CIRCUIT SIMULATION; CMOS INTEGRATED CIRCUITS; NEUTRONS; THREE DIMENSIONAL;

CHARGE COLLECTION; MULTIPLE CELL UPSETS (MCU); TRIPLE WELLS;

STATIC RANDOM ACCESS STORAGE;

EID: 37249088963     PISSN: 00189499     EISSN: None     Source Type: Journal    
DOI: 10.1109/TNS.2007.908147     Document Type: Conference Paper

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